11.3 Operation ........................................................................................................................... 412
11.3.1
Overview......................................................................................................... 412
11.3.2
Output Timing................................................................................................. 413
11.3.3
Normal TPC Output........................................................................................ 414
11.3.4
Non-Overlapping TPC Output........................................................................ 416
11.3.5
TPC Output Triggering by Input Capture....................................................... 418
11.4
Usage Notes.................................................................................................................... 419
11.4.1
Operation of TPC Output Pins........................................................................ 419
11.4.2
Note on Non-Overlapping Output.................................................................. 419
Section 12
12.1
Watchdog Timer
........................................................................................ 421
Overview......................................................................................................................... 421
12.1.1
Features........................................................................................................... 421
12.1.2
Block Diagram................................................................................................ 422
12.1.3
Pin Configuration............................................................................................ 422
12.1.4
Register Configuration.................................................................................... 423
Register Descriptions...................................................................................................... 424
12.2.1
Timer Counter (TCNT)................................................................................... 424
12.2.2
Timer Control/Status Register (TCSR)........................................................... 425
12.2.3
Reset Control/Status Register (RSTCSR) ...................................................... 427
12.2.4
Notes on Register Access ............................................................................... 429
Operation ........................................................................................................................ 431
12.3.1
Watchdog Timer Operation............................................................................. 431
12.3.2
Interval Timer Operation ................................................................................ 432
12.3.3
Timing of Setting of Overflow Flag (OVF).................................................... 433
12.3.4
Timing of Setting of Watchdog Timer Reset Bit (WRST) ............................. 434
Interrupts......................................................................................................................... 435
Usage Notes.................................................................................................................... 435
12.2
12.3
12.4
12.5
Section 13
13.1
Serial Communication Interface
........................................................... 437
Overview......................................................................................................................... 437
13.1.1
Features........................................................................................................... 437
13.1.2
Block Diagram................................................................................................ 439
13.1.3
Input/Output Pins............................................................................................ 440
13.1.4
Register Configuration.................................................................................... 440
Register Descriptions...................................................................................................... 441
13.2.1
Receive Shift Register (RSR) ......................................................................... 441
13.2.2
Receive Data Register (RDR)......................................................................... 441
13.2.3
Transmit Shift Register (TSR)........................................................................ 442
13.2.4
Transmit Data Register (TDR)........................................................................ 442
13.2.5
Serial Mode Register (SMR).......................................................................... 443
13.2