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Section 15 Serial Communication Interface (SCI, IrDA)................................ 379
15.1 Overview ....................................................................................................................... 379
15.1.1 Features ............................................................................................................ 379
15.1.2 Block Diagram.................................................................................................. 381
15.1.3 Pin Configuration.............................................................................................. 382
15.1.4 Register Configuration...................................................................................... 383
15.2 Register Descriptions ..................................................................................................... 384
15.2.1 Receive Shift Register (RSR)............................................................................ 384
15.2.2 Receive Data Register (RDR) ........................................................................... 384
15.2.3 Transmit Shift Register (TSR) .......................................................................... 385
15.2.4 Transmit Data Register (TDR) .......................................................................... 385
15.2.5 Serial Mode Register (SMR) ............................................................................. 386
15.2.6 Serial Control Register (SCR) ........................................................................... 389
15.2.7 Serial Status Register (SSR).............................................................................. 393
15.2.8 Bit Rate Register (BRR) ................................................................................... 397
15.2.9 Serial Interface Mode Register (SCMR)............................................................ 405
15.2.10 Module Stop Control Register (MSTPCR) ...................................................... 406
15.2.11 Keyboard Comparator Control Register (KBCOMP)....................................... 408
15.3 Operation ....................................................................................................................... 409
15.3.1 Overview .......................................................................................................... 409
15.3.2 Operation in Asynchronous Mode ..................................................................... 411
15.3.3 Multiprocessor Communication Function.......................................................... 422
15.3.4 Operation in Synchronous Mode ....................................................................... 430
15.3.5 IrDA Operation................................................................................................. 439
15.4 SCI Interrupts................................................................................................................. 442
15.5 Usage Notes ................................................................................................................... 443
Section 16 I
2C Bus Interface [H8S/2138 Series Option] ................................. 447
16.1 Overview ....................................................................................................................... 447
16.1.1 Features ............................................................................................................ 447
16.1.2 Block Diagram.................................................................................................. 449
16.1.3 Input/Output Pins.............................................................................................. 450
16.1.4 Register Configuration...................................................................................... 451
16.2 Register Descriptions ..................................................................................................... 452
16.2.1 I
2C Bus Data Register (ICDR)........................................................................... 452
16.2.2 Slave Address Register (SAR) .......................................................................... 455
16.2.3 Second Slave Address Register (SARX) ........................................................... 457
16.2.4 I
2C Bus Mode Register (ICMR) ........................................................................ 458
16.2.5 I
2C Bus Control Register (ICCR) ...................................................................... 462
16.2.6 I
2C Bus Status Register (ICSR) ......................................................................... 469
16.2.7 Serial/Timer Control Register (STCR) .............................................................. 474
16.2.8 DDC Switch Register (DDCSWR) .................................................................... 475