ii
4.2.2
Prescaler.............................................................................................................................
Oscillator Halt Function.....................................................................................................
Usage Notes.......................................................................................................................
4.5.1
Oscillator Usage Notes.........................................................................................
4.5.2
Notes on Board Design.........................................................................................
4.5.3
Spread Spectrum Clock Generator Usage Notes.................................................. 85
External Clock Input Method...............................................................................
82
83
83
83
83
84
4.3
4.4
4.5
Section 5
5.1
Exception Processing
.....................................................................................
Overview............................................................................................................................ 87
5.1.1
Types of Exception Processing and Priority.........................................................
5.1.2
Exception Processing Operations.........................................................................
5.1.3
Exception Processing Vector Table...................................................................... 89
Resets.................................................................................................................................
5.2.1
Power-On Reset.................................................................................................... 91
5.2.2
Manual Reset........................................................................................................ 91
Address Errors...................................................................................................................
5.3.1
Address Error Exception Processing.................................................................... 93
Interrupts............................................................................................................................ 93
5.4.1
Interrupt Priority Level.........................................................................................
5.4.2
Interrupt Exception Processing.............................................................................
Exceptions Triggered by Instructions................................................................................ 94
5.5.1
Trap Instructions...................................................................................................
5.5.2
Illegal Slot Instructions.........................................................................................
5.5.3
General Illegal Instructions...................................................................................
When Exception Sources Are Not Accepted.....................................................................
5.6.1
Immediately after a Delayed Branch Instruction.................................................. 96
5.6.2
Immediately after an Interrupt-Disabled Instruction............................................ 96
Stack Status after Exception Processing Ends...................................................................
Notes on Use...................................................................................................................... 98
5.8.1
Value of Stack Pointer (SP).................................................................................. 98
5.8.2
Value of Vector Base Register (VBR) .................................................................
5.8.3
Address Errors Caused by Stacking of Address Error Exception Processing...... 98
87
87
88
5.2
90
5.3
92
5.4
94
94
5.5
95
95
96
96
5.6
5.7
5.8
97
98
Section 6
6.1
Interrupt Controller (INTC)
.........................................................................
Overview............................................................................................................................ 99
6.1.1
Features.................................................................................................................
6.1.2
Block Diagram...................................................................................................... 99
6.1.3
Pin Configuration ................................................................................................. 101
6.1.4
Register Configuration ......................................................................................... 101
Interrupt Sources................................................................................................................ 102
6.2.1
NMI Interrupts...................................................................................................... 102
6.2.2
User Break Interrupt............................................................................................. 102
99
99
6.2