SSR—Serial Status Register
Bit
H'B4
SCI0
0
MPBT
0
R/W
Initial value
Read/Write
7
TDRE
1
R/(W)
6
RDRF
0
R/(W)
5
ORER
0
R/(W)
4
FER/ERS
0
R/(W)
3
PER
0
R/(W)
2
TEND
1
R
1
MPB
0
R
*
*
*
*
*
Multiprocessor bit transfer
0
Multiprocessor bit value in
transmit data is 0
1
Multiprocessor bit value in
transmit data is 1
Transmit end
0
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
The DMAC writes data in TDR.
1
[Setting conditions]
Reset or transition to standby mode.
TE is cleared to 0 in SCR and FER/ERS is
cleared to 0.
TDRE is 1 when last bit of 1-byte serial character
is transmitted.
Multiprocessor bit
0
Multiprocessor bit value in
receive data is 0
1
Multiprocessor bit value in
receive data is 1
Parity error
0
[Clearing conditions]
Reset or transition to standby mode.
Read PER when PER = 1, then write 0
in PER.
1
[Setting condition]
Parity error: (parity of receive data does
not match parity setting O/E bit in SMR)
Framing error (for SCI0)
0
[Clearing conditions]
Reset or transition to standby mode.
Read FER when FER = 1, then write 0 in FER.
1
[Setting condition]
Framing error (stop bit is 0)
Error signal status (for smart card interface)
0
[Clearing conditions]
Reset or transition to standby mode.
Read ERS when ERS = 1, then write 0 in ERS.
1
[Setting condition]
A low error signal is received.
Overrun error
0
[Clearing conditions]
Reset or transition to standby mode.
Read ORER when ORER = 1, then write 0 in
ORER.
1
[Setting condition]
Overrun error (reception of next serial data
ends when RDRF = 1)
Receive data register full
0
[Clearing conditions]
Reset or transition to standby mode.
Read RDRF when RDRF = 1, then write 0 in
RDRF.
The DMAC reads data from RDR.
1
[Setting condition]
Serial data is received normally and transferred
from RSR to RDR
Transmit data register empty
0
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
The DMAC writes data in TDR.
1
[Setting conditions]
Reset or transition to standby mode.
TE is 0 in SCR
Data is transferred from TDR to TSR, enabling new
data to be written in TDR.
Note: Only 0 can be written, to clear the flag.
*
800