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Hitachi Embedded Workshop User Manual
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Section 2 Simulator/Debugger Functions
This section describes the functions of the H8S, H8/300 series simulator/debugger.
2.1
Features
Since the simulator/debugger runs on a host computer, software debugging can start without using an actual
user system, thus reducing overall system development time.
The simulator/debugger performs a simulation to calculate the number of instruction execution cycles for a
program, thus enabling performance evaluation without using an actual user system.
The simulator/debugger offers the following functions that enable efficient program testing and debugging.
The ability to handle all of the H8S, H8/300 series CPUs
Functions to stop or continue execution when an error occurs during user program execution
Profile data acquisition and function-unit performance measurement
A comprehensive set of break functions (Pseudo-interrupts are also possible)
Functions to set or edit memory maps
Functions to display function call history
Coverage information is displayed in the C/C++ or assembly-source level
Visual debugging functions provided through the display of images or waveforms
The breakpoints, memory map, performance, and trace can be set through the dialog boxes under Windows.
Environments corresponding to each memory map of the H8S, H8/300 series microcomputers can be set
through the dialog box.
Intuitive user interface
Online help
Common display and operationality
2.2
Target User Program
Load modules in the Elf/Dwarf2 format can be symbolically debugged with the simulator/debugger. Load
modules in other formats can be downloaded, and their instructions can be executed, however, they cannot be
symbolically debugged. For details, refer to section 4.10, Elf/Dwarf2 Support.
2.3
Simulation Range
The simulator/debugger provides simulation functions for the H8/300, H8/300L, H8/300H, H8S/2600, and
H8S/2000 series microcomputers.
The simulator/debugger supports the following H8S, H8/300 series microcomputer functions:
All CPU instructions
Exception processing
Registers
All address areas
CPU modes shown in table 2.1