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參數(shù)資料
| 型號： | HD64646 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | LCTC (LCD Timing Controller) |
| 中文描述： | LCTC（LCD定時控制器） |
| 文件頁數(shù)： | 5/50頁 |
| 文件大小： | 156K |
| 代理商： | HD64646 |
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HD64645/64646
5
Pin Functions
Power Supply (V
CC
1, V
CC
2, GND)
Power Supply Pin (+5 V):
Connect V
CC
1 and V
CC
2 with +5V power supply circuit.
Ground Pin (0 V):
Connect GND1 and GND2 with 0V.
LCD Interface
LCD Up Panel Data (LU0–LU3), LCD Down Panel Data (LD0–LD3):
LU0–LU3 and LD0–LD3 output
LCD data as shown in Table 1.
Clock One (CL1):
CL1 supplies timing clocks for display data latch.
Clock Two (CL2):
CL2 supplies timing clock for display data shift.
First Line Marker (FLM):
FLM supplies first line marker.
M (M):
M converts liquid crystal drive output to AC.
Memory Interface
Memory Address (MA0–MA15):
MA0–MA15 supply the display memory address.
Raster Address (RA0–RA4):
RA0–RA4 supply the raster address.
Memory Data (MD0–MD7):
MD0–MD7 receive the character dot data or bit-mapped data.
Memory Data (MD8–MD15):
MD8–MD15 receive attribute code data or bit-mapped data.
MPU Interface
Data Bus (DB0–DB7):
DB0–DB7 send/receive data as a three-state I/O common bus.
Chip Select (
CS
):
CS
selects a chip. Low level enables MPU read/write of the LCTC internal registers.
Write (
WR
):
WR
receives MPU write strobe.
Read (
RD
):
RD
receives MPU read strobe.
Register Select (RS):
RS selects registers. (Refer to Table 4.)
Reset (
RES
):
RES
performs external reset of the LCTC. Low level of
RES
stops and zero-clears the LCTC
internal counter. No register contents are affected.
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