HD64645/64646
15
Registers
Table 4 shows the register mapping. Table 5 describes their function. Table 6 shows the differences
between CRTC and LCTC registers.
Table 4
Registers Mapping
Address
Register
Reg.
No.
Data Bit
CS RS
4 3 2 1 0
Register Name
Program Unit
Symbol
R/W
7
6
5
4
3
2
1
0
1
—
—————
Invalid
—
—
—
0
0
————— AR
Address Register
—
—
W
0
1
0 0 0 0 0
R0
Horizontal total characters
Character*
3
Nht
W
0
1
0 0 0 0 1
R1
Horizontal displayed char.s
Character
Nhd
W
0
1
0 1 0 0 1
R9
Maximum raster address
Raster
Nr
W
0
1
0 1 0 1 0
R10 Cursor start raster
Raster*
4
Ncs
W
B
P
0
1
0 1 0 1 1
R11
Cursor end raster
Raster
Nce
W
0
1
0 1 1 0 0
R12 Start address (H)
Memory address
—
R/W
0
1
0 1 1 0 1
R13 Start address (L)
Memory address
—
R/W
0
1
0 1 1 1 0
R14 Cursor address (H)
Memory address
—
R/W
0
1
0 1 1 1 1
R15 Cursor address (L)
Memory address
—
R/W
0
1
1 0 0 1 0
R18 Horizontal virtual screen width Character
Nir
W
0
1
1 0 0 1 1
R19 Multiplexing duty ratio (H)
Raster*
3
Ndh
W
0
1
1 0 1 0 0
R20 Multiplexing duty ratio (L)
Raster*
3
Ndl
W
0
1
1 0 1 0 1
R21 Display start raster
Raster
Nsr
W
0
1
1 0 1 1 0
—*
5
—
W
ON/ G/C
WIDE
BLE AT
OFF
Notes: 1.
: Invalid data bits
R/W indicates whether write access or read access is enabled to/from each register.
W:
Only write accessible
R/W:Both read and write accessible
The “value to be specified minus 1” should be programmed in these registers: R0, R1 and R20.
Data bits 5 and 6 of cursor start register control the cursor status as shown below (for more
details, refer to page 27).
2.
3.
4.
B
P
Cursor Blink Mode
0
0
1
1
0
1
0
1
Cursor on; without blinking
Cursor off
Blinking once every 32 frames
Blinking once every 64 frames
5.
6.
The OR of mode pin status and mode register data determines the mode.
Registers R2–R8, R16, and R17 are not assigned for the LCTC. Programming to these
registers will be ignored.