參數(shù)資料
型號： HD6435368SV
廠商： Hitachi,Ltd.
英文描述： Single-Chip Microcomputer
中文描述： 單片機(jī)
文件頁數(shù)： 13/487頁
文件大?。?/td> 1408K
代理商： HD6435368SV
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Figures
1-1
1-2
1-3
1-4
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10 (a) External Access Cycle (Read Access) ·············································································68
3-10 (b) External Access Cycle (Write Access) ············································································69
3-11
Operating States ···············································································································70
3-12
State Transitions ··············································································································71
3-13
Bus-Right Release Cycle (During On-chip Memory Access Cycle) ·······························73
3-14
Bus-Right Release Cycle (During External Access Cycle) ·············································74
3-15
Bus-Right Release Cycle (During Internal CPU Operation) ···········································75
4-1
Types of Factors Causing Exception Handling ·······························································81
4-2
Reset Vector ·····················································································································84
4-3
Reset Sequence (Minimum Mode, On-Chip Memory) ···················································85
4-4
Reset Sequence (Maximum Mode, External Memory) ···················································86
4-5
Interrupt Sources (and Number of Interrupt Types) ························································90
5-1
Interrupt Controller Block Diagram ················································································98
5-2
Interrupt Handling Flowchart ························································································107
5-3 (a)
Stack before and after Interrupt Exception-Handling (Minimum Mode) ······················108
5-3 (b) Stack before and after Interrupt Exception-Handling (Maximum Mode) ·····················109
5-4
Interrupt Sequence (Minimum Mode, On-Chip Memory) ············································110
5-5
Interrupt Sequence (Maximum Mode, External Memory) ············································111
6-1
Block Diagram of Data Transfer Controller ··································································114
6-2
Flowchart of Data Transfer Cycle ··················································································119
6-3
DTC Vector Table ··········································································································120
6-4
DTC Vector Table Entry ································································································121
6-5
Order of Register Information ·······················································································122
6-6
Use of DTC to Receive Data via Serial Communication Interface 1 ····························126
7-1
Block Diagram of Wait-State Controller ·······································································128
Block Diagram ···················································································································5
Pin Arrangement (CP-84, Top View) ················································································6
Pin Arrangement (CG-84, Top View) ················································································7
Pin Arrangement (FP-80A, TFP-80C, Top View) ·····························································8
H8/534 Memory Map in Each Operating Mode ······························································28
H8/536 Memory Map in Each Operating Mode ······························································29
CPU Operating Modes ·····································································································32
Registers in the CPU ········································································································33
Stack Pointer ····················································································································34
Combinations of Page Registers with Other Registers ····················································38
Short Absolute Addressing Mode and Base Register ······················································39
On-Chip Memory Access Timing ····················································································64
Pin States during Access to On-Chip Memory ································································65
Register Field Access Timing ··························································································66
Pin States during Register Field Access ··········································································67
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