Table 5-2 Interrupts, Vectors, and Priorities
*
If two or more interrupts are requested simultaneously, they are handled in order of priority level,
as set in registers IPRA to IPRF. If they have the same priority level because they are requested
from the same on-chip supporting module, they are handled in a fixed priority order within the
module. If they are requested from different modules to which the same priority level is
assigned, they are handled in the order indicated in the right-hand column.
Assignable
Priority
Levels
(Initial
Level)
8(8)
7 to 0
(0)
7 to 0
(0)
7 to 0
(0)
7 to 0
(0)
7 to 0
(0)
Priority
among
Interrupts
on Same
Level
*
High
Vector Table
Entry Address
Minimum
Mode
H'16 - H'17
H'40 - H'41
H'42 - H'43
H'48 - H'49
Priority
within
Module
—
1
0
—
IPR
Bits
—
IPRA
bits 6 to 4
IPRA
bits 2 to 0
IPRB
bits 6 to 4
IPRB
bits 2 to 0
IPRC
bits 6 to 4
Maximum
Mode
H'2C - H'2F
H'80 - H'83
H'84 - H'87
H'90 - H'93
Interrupt
NMI
IRQ
0
Interval timer
IRQ
1
IRQ
2
IRQ
3
IRQ
4
IRQ
5
FRT1
1
0
1
0
3
2
1
0
3
2
1
0
3
2
1
0
2
1
0
2
1
0
2
1
0
—
H'50 - H'51
H'52 - H'53
H'58 - H'59
H'5A - H'5B
H'60 - H'61
H'62 - H'63
H'64 - H'65
H'66 - H'67
H'68 - H'69
H'6A - H'6B
H'6C - H'6D
H'6E - H'6F
H'70 - H'71
H'72 - H'73
H'74 - H'75
H'76 - H'77
H'78 - H'79
H'7A - H'7B
H'7C - H'7D
H'80 - H'81
H'82 - H'83
H'84 - H'85
H'88 - H'89
H'8A - H'8B
H'8C - H'8D
H'90 - H'91
H'A0 - H'A3
H'A4 - H'A7
H'B0 - H'B3
H'B4 - H'B7
H'C0 - H'C3
H'C4 - H'C7
H'C8 - H'CB
H'CC - H'CF
H'D0 - H'D3
H'D4 - H'D7
H'D8 - H'DB
H'DC - H'DF
H'E0 - H'E3
H'E4 - H'E7
H'E8 - H'EB
H'EC - H'EF
H'F0 - H'F3
H'F4 - H'F7
H'F8 - H'FB
H'100 - H'103
H'104 - H'107
H'108 - H'10B
H'110 - H'113
H'114 - H'117
H'118 - H'11B
H'120 - H'123
ICI
OCIA
OCIB
FOVI
ICI
OCIA
OCIB
FOVI
ICI
OCIA
OCIB
FOVI
CMIA
CMIB
OVI
ERI
RXI
TXI
ERI
RXI
TXI
ADI
FRT2
7 to 0
(0)
IPRC
bits 2 to 0
FRT3
7 to 0
(0)
IPRD
bits 6 to 4
8-bit
timer
7 to 0
(0)
IPRD
bits 2 to 0
SCI1
7 to 0
(0)
IPRE
bits 6 to 4
SCI2
7 to 0
(0)
IPRE
bits 2 to 0
A/D
converter
7 to 0
(0)
IPRF
bits 6 to 4
Low
103