
register list: A byte in which bits indicate general registers as follows
#VEC: Four bits designating a vector number from 0 to 15. The vector numbers correspond to
addresses of entries in the exception vector table as follows:
Vector Address
Vector Address
#VEC Minimum Mode
0
H'0020 – H'0021
1
H'0022 – H'0023
2
H'0024 – H'0025
3
H'0026 – H'0027
4
H'0028 – H'0029
5
H'002A – H'002B
6
H'002C – H'002D
7
H'002E – H'002F
Maximum Mode
H'0040 – H'0043
H'0044 – H'0047
H'0048 – H'004B
H'004C – H'004F
H'0050 – H'0053
H'0054 – H'0057
H'0058 – H'005B
H'005C – H'005F
#VEC Minimum Mode
8
H'0030 – H'0031
9
H'0032 – H'0033
10
H'0034 – H'0035
11
H'0036 – H'0037
12
H'0038 – H'0039
13
H'003A – H'003B
14
H'003C – H'003D
15
H'003E – H'003F
Maximum Mode
H'0060 – H'0063
H'0064 – H'0067
H'0068 – H'006B
H'006C – H'006F
H'0070 – H'0073
H'0074 – H'0077
H'0078 – H'007B
H'007C – H'007F
Examples of machine-language coding
Example 1:
ADD:G.B @R0, R1
EA Field
1101Szrrr
11010000
OP Field
00100r
d
r
d
r
d
00100 0 0 1
H'D021
Notes
Table A-1 (a)
Machine code
Machine code for ADD:G.B @Rs, Rd
Sz = 0 (byte)
Rs = R0, Rd = R1
Example 2:
ADD:G.W @H'11:8, R1
EA Field
OP Field
Notes
Table A-1 (a)
Machine code
0000Sz101
0000 1 101
00010001 00100r
d
r
d
r
d
00010001 00100 0 0 1
H'0D1121
Machine code for ADD:G.W @aa:8, Rd
Sz = 1 (word)
aa = H'11, Rd = R1
Bit
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
371