參數(shù)資料
型號(hào)： HD6435328CP
廠商： Hitachi,Ltd.
英文描述： Manual Gives a Hardware Description
中文描述： 手冊(cè)給出硬件描述
文件頁數(shù)： 17/459頁
文件大?。?/td> 1032K
代理商： HD6435328CP
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C-7 (d) Schematic Diagram of Port 7, Pins P7
4
, P7
5
and P7
6
····················································421
C-7 (e) Schematic Diagram of Port 7, Pin P7
7
··········································································422
C-8
Schematic Diagram of Port 8 ·························································································423
C-9 (a) Schematic Diagram of Port 9, Pins P9
0
and P9
1
···························································424
C-9 (b) Schematic Diagram of Port 9, Pins P9
2
, P9
3
and P9
4
····················································425
C-9 (c) Schematic Diagram of Port 9, Pin P9
5
··········································································426
C-9 (d) Schematic Diagram of Port 9, Pin P9
6
··········································································427
C-9 (e) Schematic Diagram of Port 9, Pin P9
7
··········································································428
E-1
Reset during Memory Access (Mode 1) ········································································435
E-2
Reset during Memory Access (Mode 1) ········································································436
E-3
Reset during Memory Access (Mode 2) ········································································438
E-4
Reset during Memory Access (Mode 2) ········································································439
E-5
Reset during Memory Access (Mode 3) ········································································441
E-6
Reset during Memory Access (Mode 3) ········································································442
E-7
Reset during Memory Access (Mode 4) ········································································444
E-8
Reset during Memory Access (Mode 4) ········································································445
E-9
Reset during Memory Access (Mode 7) ········································································446
E-10
Reset during Memory Access (Mode 7) ········································································447
G-1
Package Dimensions (CP-84) ························································································451
G-2
Package Dimensions (CG-84) ·······················································································451
G-3
Package Dimensions (FP-80A) ······················································································452
Tables
1-1
1-2
1-3
1-4
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
Features ······························································································································2
Pin Arrangements in Each Operating Mode (CP-84, CG-84) ···········································8
Pin Arrangements in Each Operating Mode (FP-80A) ····················································12
Pin Functions ···················································································································16
Operating Modes ·············································································································23
Mode Control Register ····································································································29
Interrupt Mask Levels ······································································································36
Interrupt Mask Bits after an Interrupt is Accepted ··························································36
Initial Values of Registers ································································································41
General Register Data Formats ························································································42
Data Formats in Memory ·································································································43
Data Formats on the Stack ·······························································································44
Addressing Modes ···········································································································46
Effective Address Calculation ·························································································47
Instruction Classification ·································································································50
Data Transfer Instructions ·······························································································52
Arithmetic Instructions ····································································································53
Logic Operation Instructions ···························································································54
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