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| 型號(hào)： | HD6433837SH |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁(yè)數(shù)： | 125/194頁(yè) |
| 文件大小： | 2303K |
| 代理商： | HD6433837SH |
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4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
The register field of the instruction specifies a 16-bit general register containing the address of
the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for
MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is decremented by
1 or 2 to obtain the address of the operand in memory. The register retains the decremented
value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original
contents of the register must be even.
5. Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit
manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR
instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is
H'FF00 to H'FFFF (65280 to 65535).
6. Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second
byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can
contain 16-bit immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit
manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number.
7. Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR
instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and
added to the program counter contents to generate a branch destination address. The possible
branching range is –126 to +128 bytes (–63 to +64 words) from the current address. The
displacement should be an even number.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HD6433837SL | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:single-chip microcomputers |
| HD6433837SX | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:single-chip microcomputers |
| HD6433837U | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Microcomputer Development Environment System H8S.H8/300 Series High-Performance Embedded Workshop 2 User＇s Manual/Cross tool |
| HD6433837UF | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:Single-Chip Microcomputer |
| HD6433837UH | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:Single-Chip Microcomputer |
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