
Rev. 4.00, 03/04, page xxiii of xxviii
Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter ...........................................................................252
Figure 16.2 A/D Conversion Timing..........................................................................................258
Figure 16.3 External Trigger Input Timing ................................................................................259
Figure 16.4 A/D Conversion Accuracy Definitions (1)..............................................................260
Figure 16.5 A/D Conversion Accuracy Definitions (2)..............................................................261
Figure 16.6 Analog Input Circuit Example.................................................................................262
Section 17 EEPROM
Figure 17.1 Block Diagram of EEPROM...................................................................................264
Figure 17.2 EEPROM Bus Format and Bus Timing ..................................................................266
Figure 17.3 Byte Write Operation ..............................................................................................269
Figure 17.4 Page Write Operation..............................................................................................269
Figure 17.5 Current Address Read Operation.............................................................................271
Figure 17.6 Random Address Read Operation...........................................................................271
Figure 17.7 Sequential Read Operation (when current address read is used).............................272
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Figure 18.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit....276
Figure 18.2 Operational Timing of Power-On Reset Circuit......................................................279
Figure 18.3 Operational Timing of LVDR Circuit.....................................................................280
Figure 18.4 Operational Timing of LVDI Circuit.......................................................................281
Figure 18.5 Timing for Operation/Release of Low-Voltage Detection Circuit..........................282
Section 19 Power Supply Circuit
Figure 19.1 Power Supply Connection when Internal Step-Down Circuit is Used....................283
Figure 19.2 Power Supply Connection when Internal Step-Down Circuit is Not Used .............284
Section 21 Electrical Characteristics
Figure 21.1 System Clock Input Timing.....................................................................................331
Figure 21.2
RES
Low Width Timing..........................................................................................331
Figure 21.3 Input Timing............................................................................................................331
Figure 21.4 I
2
C Bus Interface Input/Output Timing...................................................................332
Figure 21.5 SCK3 Input Clock Timing.......................................................................................332
Figure 21.6 SCI Input/Output Timing in Clocked Synchronous Mode......................................333
Figure 21.7 EEPROM Bus Timing.............................................................................................333
Figure 21.8 Output Load Circuit.................................................................................................334
Appendix B I/O Port Block Diagrams
Figure B.1 Port 1 Block Diagram (P17).....................................................................................365
Figure B.2 Port 1 Block Diagram (P16 to P14)..........................................................................366
Figure B.3 Port 1 Block Diagram (P12, P11).............................................................................367
Figure B.4 Port 1 Block Diagram (P10).....................................................................................368
Figure B.5 Port 2 Block Diagram (P22).....................................................................................369
Figure B.6 Port 2 Block Diagram (P21).....................................................................................370