i
Contents
Section 1
1.1
1.2
1.3
Overview
............................................................................................................
Overview............................................................................................................................
Block Diagram...................................................................................................................
Pin Assignments and Functions.........................................................................................
1.3.1
Pin Arrangement...................................................................................................
1.3.2
Pin Functions........................................................................................................
1
1
5
6
6
7
Section 2
2.1
CPU
.....................................................................................................................
Overview............................................................................................................................ 19
2.1.1
Features.................................................................................................................
2.1.2
Address Space.......................................................................................................
2.1.3
Register Configuration.......................................................................................... 20
Register Descriptions.........................................................................................................
2.2.1
General Registers.................................................................................................. 21
2.2.2
Control Registers.................................................................................................. 21
2.2.3
Initial Register Values .......................................................................................... 22
Data Formats...................................................................................................................... 23
2.3.1
Data Formats in General Registers.......................................................................
2.3.2
Memory Data Formats.......................................................................................... 25
Addressing Modes.............................................................................................................. 26
2.4.1
Addressing Mode.................................................................................................. 26
2.4.2
Calculation of Effective Address.......................................................................... 28
Instruction Set.................................................................................................................... 32
2.5.1
Data Transfer Instructions .................................................................................... 34
2.5.2
Arithmetic Operations .......................................................................................... 36
2.5.3
Logic Operations .................................................................................................. 37
2.5.4
Shift Operations.................................................................................................... 37
2.5.5
Bit Manipulations.................................................................................................. 39
2.5.6
Branching Instructions.......................................................................................... 44
2.5.7
System Control Instructions.................................................................................. 46
2.5.8
Block Data Transfer Instruction............................................................................ 47
CPU States .........................................................................................................................
2.6.1
Overview...............................................................................................................
2.6.2
Program Execution State ...................................................................................... 50
2.6.3
Exception-Handling State.....................................................................................
2.6.4
Power-Down State................................................................................................ 51
Access Timing and Bus Cycle...........................................................................................
2.7.1
Access to On-Chip Memory (RAM and ROM).................................................... 51
2.7.2
Access to On-Chip Register Field and External Devices.....................................
19
19
20
2.2
21
2.3
24
2.4
2.5
2.6
49
49
50
2.7
51
53