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參數(shù)資料
| 型號： | HD61830 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | LCDC (LCD Timing Controller) |
| 中文描述： | LCDC（LCD定時控制器） |
| 文件頁數(shù)： | 12/43頁 |
| 文件大?。?/td> | 173K |
| 代理商： | HD61830 |
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HD61830/HD61830B
12
6. Set Display Start Low Order Address:
(Execution time: 4
μ
s) Cause display start addresses to be
written in the display start address registers. The display start address indicates a RAM address at which the
data displayed at the top left end on the screen is stored. In the graphic mode, the start address is composed
of high/low order 16 bits. In the character display, it is composed of the lower 4 bits of high order address
(DB3–DB0) and 8 bits of low order address. The upper 4 bits of high order address are ignored.
Register
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Instruction reg.
0
1
0
0
0
0
1
0
0
0
Display start address reg.
(low order byte)
0
0
(Start low order address) binary
Set Display Start High Order Address
Register
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Instruction reg.
0
1
0
0
0
0
1
0
0
1
Display start address reg.
(high order byte)
0
0
(Start high order address) binary
7. Set Cursor Address (Low Order) (RAM Write Low Order Address):
(Execution time: 4
μ
s) Cause
cursor addresses to be written in the cursor address counters. The cursor address indicates an address for
sending or receiving display data and character codes to or from the RAM.
That is, data at the address specified by the cursor address are read/written. In the character mode, the
cursor is displayed at the character specified by the cursor address.
A cursor address consists of the low-order address (8 bits) and the high-order address (8 bits). Satisfy the
following requirements setting the cursor address (Table 2).
The cursor address counter is a 16-bit up-counter with set and reset functions. When bit N changes from 1
to 0, bit N + 1 is incremented by 1. When setting the low order address, the LSB (bit 1) of the high order
address is incremented by 1 if the MSB (bit 8) of the low order address changes from 1 to 0. Therefore, set
both the low order address and the high order address as shown in the Table 2.
Register
R/W
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Instruction reg.
0
1
0
0
0
0
1
0
1
0
Cursor address counter
(low order byte)
0
0
(Cursor low order address) binary
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD61830B | LCDC (LCD Timing Controller) |
| HD61830B00H | LCDC (LCD Timing Controller) |
| HD6301X0 | CMOS MCU |
| HD6301X0CP | CMOS MCU |
| HD6301X0F | CMOS MCU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD61830A00H | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:LCDC (LCD Timing Controller) |
| HD61830B | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:LCDC (LCD Timing Controller) |
| HD61830B00 | 制造商:HITCHI 功能描述: |
| HD61830B00H | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:LCDC (LCD Timing Controller) |
| HD61945MP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Phase-Locked Loop |
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