HD61604/HD61605
1291
Standby Operation
Standby operation with low power consumption can be activated when pin SB is used. Normal operation
of the LSI is activated when pin SB is low level, and the LSI goes into the standby state when pin SB is
high level. The standby state of the LSI is as follows:
1. LCD driver is stopped (LCD is off).
2. Display data and operating mode are held.
3. The operation is suspended while display changes (while READY is outputting low). In this case,
READY outputs high within 10.5 clocks or 3.5 clocks after release from the standby mode.
4. Oscillation is stopped.
When this mode is not used, connect pin SB to VSS.
Multichip Operation
When an LCD is driven with two or more chips, the driving timing of the LCD must be synchronized. In
this case, the chips are synchronized with each other by using SYNC input. If SYNC input is high, the
LCD driver timing circuit is reset. Apply high pulse to the SYNC input after the operating mode is set.
A high pulse to the SYNC input changes the mode setting data. (The OFF/ON bit is set and the READY
bit is reset. See (3) Mode Setting Data in “Input Data Formats.”) Transfer the mode setting data into the
LSI after every SYNC operation.
If a power on reset signal is applied to the SYNC pin, the LCD can be off-state when the power is turned
on.
When SYNC input is not used, connect pin SYNC to VSS.
When SB input is used, after standby mode is released, high pulse must be applied to the SYNC input,
and mode setting data must be set again.
Restriction on Usage
Minimize the noise by inserting a noise bypass capacitor (
≥
1 μF) between VDD and VSS pins. (Insert
one as near chip as possible.)