參數(shù)資料
型號: HD49801FB
廠商: Electronic Theatre Controls, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processing IC for CCD Cameras
中文描述: 數(shù)字信號處理集成電路CCD相機(jī)
文件頁數(shù): 30/43頁
文件大?。?/td> 185K
代理商: HD49801FB
A/D input data (line delay memory R/W) transfer protocol
Line delay memory R/W setting example
The relationship between the CCD sensor complementary color signals (Wrn, Gbn, Grn, and Wrn) and
state data A7 (a, b, c, d) is determined by the relationship between the HGI input and the start address.
HGI is a line determination input, and when high, the two complementary color signals correspond to (a,
b), and when low, they correspond to (c, d).
HREFI
ADI1 to ADI9
SCKI
D2
D768
Start address
(state data A14 to A1)
Stop address
(state data A14 to A2)
State data A16 DCKC:
State data A16 HCKC: 1: Positive phase (HREFI falling edge detected on the rising edge of SCKI)
0: Reverse phase (HREFI falling edge detected on the falling edge of SCKI)
1: Positive phase (ADI1 to ADI9 latched on the rising edge of SCKI)
0: Reverse phase (ADI1 to ADI9 latched on the falling edge of SCKI)
D1
SCKI
HREFI
HREFI
falling edge
detection
Memory stop counter clear
an
ADI1 to ADI9 (HGI = H)
bn
an + 1 bn + 1
an+m bn+m
(For example, Wrn Gbn)
cn
ADI1 to ADI9 (HGI = L)
dn
cn + 1 dn + 1
cn+m dn+m
(For example, Grn Wbn)
A14 to A1 (memory start address)
A14 to A2 (memory stop address)
A16 to A1 (mode): HCKC = 1, DCKC = 1
Memory start address
Memory stop address
Valid data (max: 768)
30
HD49801FB
HD49801FB
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