參數(shù)資料
型號(hào): HD49323AF
廠商: Hitachi,Ltd.
英文描述: CDS/AGC & 10-bit A/D Converter
中文描述: 的CDS /自動(dòng)增益控制
文件頁數(shù): 8/27頁
文件大小: 104K
代理商: HD49323AF
HD49323AF-01
8
3. AGC Circuit
The AGC gain is set by means of 11-bit serial data. The setting range is –3.3 dB to 34.7 dB. Details of
the data are given in the following section.
The (–) side gain setting uses setting codes –81 to 0 in 0.0039-multiple steps, and the (+) side gain
setting uses setting codes 0 to 1023 in 0.034 dB steps.
Detailed specifications of HD49323AF-01 AGC gain setting codes
(1) To improve S/N, the AD input dynamic range has been extended to 1.4 V from the 1.0 V of the
HD49322BF.
(2) There are two AGC gain ranges: (+) side 0 to 34.7 dB linear gain amp. (0.034 dB/step), and (–) side
0 to –3.3 dB “multiple” linear gain amp. (0.0039 multiple/step).
CDS
AGC
ADC
Range
Typ 1.4V
0V = 0 code
0.7V = 511 code
1.4V = 1023 code
Output
Input
Considering the case where AGC gain is set so that the ADC output code is 511 when a 150 mV signal is
input:
The HD49322BF AGC gain setting is (code 511)/150 mV multiple = 500 mV/150 mV multiple
The HD49323AF-01 AGC gain setting is (code 511)/150 mV multiple = 700 mV/150 mV multiple
Table 2 AGC Gain (
) Setting Code Table
Code
BIN (D10 to D0) Multiple
0
000 0000 0000
1
111
111
Table 1 AGC Gain (+) Setting Code Table
Code
BIN (D10 to D0)
0
000 0000 0000
1
000 0000 0001
dB
0.000
0.034
3
000 0000 0011
0.102
2
000 0000 0010
0.068
510
511
001 1111 1110
001 1111 1111
17.34
17.37
513
010 0000 0001
17.44
512
010 0000 0000
17.41
1020
1021
011 1111 1100
011 1111 1101
34.68
34.71
1023
011 1111 1111
34.78
1022
011 1111 1110
34.75
1.000
0.996
3
111 1111 1101
0.988
2
1111 1110
0.992
1111 1111
30
31
111 1110 0010
111 1110 0001
0.883
0.879
33
111 1101 1111
0.871
32
111 1110 0000
0.875
78
79
111 1011 0010
111 1011 0001
0.695
0.691
81
111 1010 1111
0.684
80
111 1011 0000
0.688
dB
0.000
0.034
0.102
0.068
1.083
1.121
1.199
1.160
3.156
3.205
3.304
3.255
4. Offset cancel circuit
When power is turned on, offset voltages generated by CDS, AGC, ADC, and other circuits by means
of serial data control are canceled. (Refer to page 24 (Operating Sequence at Power-On).)
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