HD404818 Series
63
Bit 3
Bit 2
Bit 1
Bit 0
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
$050
$051
$052
$053
$054
$055
$056
$057
$058
$059
$05A
$05B
$05C
$05D
$05E
$05F
COM4
COM3
COM2
COM1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
Bit 3
Bit 2
Bit 1
Bit 0
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
$060
$061
$062
$063
$064
$065
$066
$067
$068
$069
$06A
$06B
$06C
$06D
$06E
$06F
COM4
COM3
COM2
COM1
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
Figure 35 Configuration of LCD RAM Area (dual port RAM)
LCD Control Register (LCR: $013):
The LCD control register is a 3-bit write-only register which
controls the blanking of the LCD, activation of the power switch, and display in watch mode/subactive
mode (table 27, figure 36).
Blank/display
Blank: Segment signal is faded regardless of the LCD RAM data.
Display: LCD RAM data is transmitted as a segment signal.
Power switch on/off
Off: Power switch is off.
On: Power switch is on and V
1
is V
CC
.
Watch mode/subactive mode display
Off: In the watch mode/subactive mode, all common/segment pins are fixed to GND, and the power
switch is off.
On: In the watch mode/subactive mode, LCD RAM data is transmitted as a segment signal.
LCD Duty-Cycle/Clock Control Register (LMR: $014):
The LCD duty-cycle/clock control register is a
write-only register which specifies four display duty cycles and the reference clock for the LCD (table 28,
figure 36).