參數(shù)資料
型號: HD40L4812
廠商: Hitachi,Ltd.
英文描述: 4-Bit Single-Chip Microcomputer(4位單片微計算機)
中文描述: 4位單片機(4位單片微計算機)
文件頁數(shù): 21/98頁
文件大?。?/td> 621K
代理商: HD40L4812
HD404818 Series
21
Table 3 Interrupt Conditions
Interrupt Source
INT
0
1
Interrupt Control Bit
INT
1
1
Timer A
Timer B
Timer C
Serial
IE
IF0
IM0
IF1
IM1
IFTA
IMTA
IFTB
IMTB
IFTC
IMTC
IFS
IMS
Note:
*
Don’t care.
1
1
1
1
1
0
0
0
0
0
*
1
0
0
0
0
*
*
1
0
0
0
*
*
*
1
0
0
*
*
*
*
1
0
*
*
*
*
*
1
Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If
an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the
second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed
onto the stack. In the third cycle, the instruction is executed after jumping to the vector address.
In each vector address, program the JMPL instruction to branch to the starting address of the interrupt
program. The IF, which caused the interrupt, must be reset by software in the interrupt program.
Instruction
cycles
1
2
3
4
5
6
Instruction
execution
Stacking;
reset of IE
Interrupt
acceptance
JMPL instruction execution
on the vector address
Instruction
execution at
starting address
of the interrupt
routine
Stacking;
vector address
generated
Figure 7 Interrupt Processing Sequence
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