參數(shù)資料
型號(hào)： HD40C4344R
廠商： Hitachi,Ltd.
英文描述： 4-bit HMCS400-series microcomputer(4位單片微計(jì)算機(jī))
中文描述： 4位HMCS400系列微電腦（4位單片微計(jì)算機(jī)）
文件頁(yè)數(shù)： 73/100頁(yè)
文件大小： 610K
代理商： HD40C4344R
HD404344R Series/HD404394 Series
73
A/D Converter
The MCU has a built-in A/D converter that uses a sequential comparison method with a register ladder. It
can perform a digital conversion with 3 or 4 analog inputs at 8-bit resolution. The following describes the
features of the A/D converter.
A/D mode register 1 (AMR1: $019) is used to select digital or analog ports (figure 53).
A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed (figure 54).
The A/D channel register (ACR: $016) is used to select an analog input channel (figure 55).
A/D conversion is started by setting the A/D start flag (ADSF: $020, bit 2) to 1. After the conversion is
completed, converted data is stored in the A/D data register, and at the same time, the A/D start flag is
cleared to 0 (figure 56).
By setting the I
AD
off flag (IAOF: $021, bit 2) to 1, the current flowing through the resistance ladder
can be cut off even in standby or active mode (figure 57).
A/D data registers (ADRL: $017, ADRU: $018) are read-only registers used to store the conversion
result. (ADRL: lower 4 bits, ADRU: upper 4 bits.) These registers cannot be cleared by a reset input.
Also, data in these registers are not guaranteed during the conversion period. After the conversion is
completed, an 8-bit result is set to these registers and kept until the next conversion starts (figures 58,
59, and 60).
Notes On Use:
Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF).
Do not write to the A/D start flag during A/D conversion.
Data in the A/D data register during A/D conversion is undefined.
Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop mode. In addition, to save power dissipation while in a stop mode, all
current flowing through the converter’s resistance ladder is cut off.
Output signal level from other ports should be fixed during A/D conversion.
The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to V
CC
. When using a
shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain
pulled up.
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