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參數(shù)資料
| 型號(hào)： | HD40A4639R |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-Bit Single-Chip Microcomputer(4位單片微計(jì)算機(jī)) |
| 中文描述： | 4位單片機(jī)（4位單片微計(jì)算機(jī)） |
| 文件頁(yè)數(shù)： | 47/133頁(yè) |
| 文件大?。?/td> | 803K |
| 代理商： | HD40A4639R |
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HD404639R Series
47
Pins D
12
and D
13
are multiplexed with peripheral function pins
STOPC
and
I NT
0
, respectively. The
peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 29).
R Ports (R0
0
–RC
0
, RD
0
–RE
0
):
49 input/output pins and 5 input pins addressed in 4-bit units. Data is input
to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions.
Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers
of the R ports are controlled by R-port data control registers (DCR0–DCRC: $030–$03C) that are mapped
to memory addresses (figure 28).
Pins R0
0
–R0
3
are multiplexed with peripheral pins
I NT
1
–INT
4
, respectively. The peripheral function modes
of these pins are selected by bits 0–3 (PMRB0–PMRB3) of port mode register B (PMRB: $024) (figure
30).
Pins R3
0
–R3
2
are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral
function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2
(TMB2: $013), bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014), and bits 0–3
(TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 31, 32, and 33).
Pins R3
3
and R4
0
are multiplexed with peripheral pins
EVNB
and EVND, respectively. The peripheral
function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C
(PMRC: $025) (figure 29).
Pins R4
1
–R4
3
are multiplexed with peripheral pins
SCK
1
, SI
1
, and SO
1
, respectively. The peripheral
function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and
bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 34 and 36.
Ports R5
1
–R5
3
are multiplexed with peripheral function pins
SCK
2
,
SI
2
, SO
2
, respectively. The function
modes of these pins can be selected by individual pins, by setting bit 3 (SM2A3) of serial mode register 2A
(SM2A: $01B), and bits 2 and 3 (PMRA2, PMRA3) of port mode register A (PMRA: $004) (figures 35 and
36).
Ports RD
0
–RD
3
are multiplexed with peripheral function pins COMP
0
–COMP
3
, respectively. The function
modes of these pins are selected by bit 3 (CER3) of the compare enable register (CER: $018).
Port RE
0
is multiplexed with peripheral function pin VC
ref
. While functioning as VC
ref
, do not use this pin
as an R port at the same time, otherwise, the MCU may malfunction.
Pull-Up or Pull-Down MOS Transistor Control:
A program-controlled pull-up or pull-down MOS
transistor is provided for each input/output pin other than input-only pins D
12
and D
13
. The on/off status of
all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off
status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding
pin—enabling on/off control of that pin alone (table 21 and figure 38).
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
How to Deal with Unused I/O Pins:
I/O pins that are not needed by the user system (floating) must be
connected to V
CC
to prevent LSI malfunctions due to noise. These pins must either be pulled up to V
CC
by
their pull-up MOS transistors or by resistors of about 100 k
or pulled down to GND by their pull-down
MOS transistors.
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