HD404889/HD404899/HD404878/HD404868 Series
25
Speed Select Reg.
Miscellaneous Reg.
Edge Select Reg.
Port Mode Reg.0
Port Mode Reg.1
Port Mode Reg.2
Port Mode Reg.3
Port Mode Reg.4
Module Standby Reg.1
Module Standby Reg.2
Timer Mode Reg.A
Timer Mode Reg.B1
Timer Mode Reg.B2
Timer Mode Reg.C1
Timer Mode Reg.C2
Timer Mode Reg.D1
Timer Mode Reg.D2
Serial Mode Reg.1
Serial Mode Reg.2
Serial Data Reg.Lower
Serial Data Reg.Upper
A/D Mode reg.
A/D Data Reg.Lower
A/D Data Reg.Middle
A/D Data Reg.Upper
LCD Control Reg.
LCD Mode Reg.
Buzzer Mode Reg.
Port D
0
~D
3
DCR
Port D
4
~D
7
DCR
Port D
8
~D
11
DCR
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
Port R8 DCR
Vreg.
$000
$040
$050
$06F
$070
$08F
$090
$38F
$390
$25F
$260
$3BF
$3C0
$3FF
RAM-mapped
register area
HD404899 Series
Memory register (MR) area
(16 digits)
LCD data area
(32 digits)
Data (464 digits)
Stack area
(64 digits)
Interrupt control bit area
Not used
W
W
W
W
W
W
W
W
W
W
W
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
W
R
R
R
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R/W
Timer-B
Timer-C
Timer-D
Not used
Register flag area
Not used
Not used
Not used
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
Timer Read Reg.B Lower
Timer Read Reg.B Upper
(TRBL)
(TRBU)
R
R
Timer Write Reg.B Lower
Timer Write Reg.B Upper
(TWBL)
(TWBU) W
W
Timer Read Reg.C Lower
Timer Read Reg.C Upper
(TRCL)
(TRCU)
R
R
Timer Write Reg.C Lower
Timer Write Reg.C Upper
(TWCL)
(TWCU) W
W
Timer Read Reg.D Lower
Timer Read Reg.D Upper
(TRDL)
(TRDU)
R
R
Timer Write Reg.D Lower
Timer Write Reg.D Upper
(TWDL)
(TWDU) W
W
$012
$013
$016
$017
$01A
$01B
*
*
Not used
Not used
V = 0 (bank = 0)
Data (464 digits)
V = 1 (bank = 1)
Data (304 digits)
(SSR)
(MIS)
(ESR)
(PMR0)
(PMR1)
(PMR2)
(PMR3)
(PMR4)
(MSR1)
(MSR2)
(TMA)
(TMB1)
(TMB2)
(TRBL/TWBL)
(TRBU/TWBU)
(TMC1)
(TMC2)
(TRCL/TWCL)
(TRCU/TWCU)
(TMD1)
(TMD2)
(TRDL/TWDL)
(TRDU/TWDU)
(SMR1)
(SMR2)
(SRL)
(SRU)
(AMR)
(ADRL)
(ADRM)
(ADRU)
(LCR)
(LMR)
(BMR)
(DCD0)
(DCD1)
(DCD2)
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
(V)
Notes: R : Read
W : Write
R/W : Read/Write
*Two registers are mapped onto the
same address ($012, $013, $016,
$017, $01A, $01B).
Figure 2 RAM Memory Map (cont)