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參數(shù)資料
| 型號(hào)： | HD4074339S |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-bit HMCS400-Series microcomputer with large-capacity memory |
| 中文描述： | 4位HMCS400系列的大容量存儲(chǔ)器微機(jī) |
| 文件頁數(shù)： | 59/78頁 |
| 文件大?。?/td> | 337K |
| 代理商： | HD4074339S |
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HD404339 Series
59
Notes on Usage
Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)
Do not write to the A/D start flag during A/D conversion
Data in the A/D data register during A/D conversion is undefined
Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop, watch, or subactive mode. In addition, to save power while in these
modes, all current flowing through the converter’s resistance ladder is cut off.
If the power supply for the A/D converter is to be different from V
CC
, connect a 0.1-
μ
F bypass capacitor
between the AV
CC
and AV
SS
pins. (However, this is not necessary when the AV
CC
pin is directly
connected to the V
CC
pin.)
The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to V
CC
. When using a
shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode registr as an analog pin will remain
pulled up.
Bit
Initial value
Read/Write
Bit name
3
0
W
AMR13
2
0
W
AMR12
0
0
W
AMR10
1
0
W
AMR11
AMR10
0
1
AN
0
A/D mode register 1 (AMR1: $019)
AMR11
0
1
AN
1
AMR12
0
1
R3
2
/AN
2
Mode Selection
R3
2
AN
2
AMR13
0
1
R3
3
/AN
3
Mode Selection
R3
3
AN
3
R3
0
/AN
0
Mode Selection
R3
0
R3
1
/AN
1
Mode Selection
R3
1
Figure 46 A/D Mode Register 1 (AMR1)
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