參數(shù)資料
型號: HD404829R
廠商: Hitachi,Ltd.
英文描述: AS Microcomputer Incorporating a LCD controller/Driver Circuit(帶LCD控制/驅(qū)動電路的微計算機)
中文描述: 由于微機安裝有LCD控制器/驅(qū)動電路(帶液晶控制/驅(qū)動電路的微計算機)
文件頁數(shù): 13/147頁
文件大?。?/td> 519K
代理商: HD404829R
HD404829R Series
13
Bit 3
Bit 2
Bit 1
Bit 0
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT
1
)
IF1
(IF of INT
1
)
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
IMAD
(IM of A/D)
IFAD
(IF of A/D)
IMTD
(IM of timer D)
IFTD
(IF of timer D)
Interrupt control bits area
IM0
(IM of INT
0
)
IF0
(IF of INT
0
)
RSP
(Reset SP bit)
IE
(Interrupt
enable flag)
ICSF
(Input capture
status flag)
IM3
(IM of
INT
3
)
IF3
(IF of INT
3
)
IM2
(IM of INT
2
)
IF2
(IF of INT
2
)
IMS
(IM of serial
interface)
IFS
(IF of serial
interface)
IM4
(IM of
INT
4
)
IF4
(IF of
INT
4
)
$000
$001
$002
$003
RAM address
$020
$021
$022
$023
Register flag area
DTON
(Direct transfer
on flag)
RAME
(RAM enable
flag)
ADSF
(A/D start flag)
WDON
(Watchdog
on flag)
ICEF
(Input capture
error flag)
LSON
(Low speed
on flag)
Not used
IF:
IM:
IE:
SP:
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
Bit 3
Bit 2
Bit 1
Bit 0
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
LSON
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
Not used
DTON
SEM/SEMD
REM/REMD
TM/TMD
Allowed
Allowed
Allowed
Not executed
Allowed
Allowed
Not executed
Allowed
Allowed
Allowed
Not executed
Inhibited
Inhibited
Inhibited
Allowed
Not executed in active mode
Used in subactive mode
Not executed
Allowed
Allowed
Not executed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
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