HD404829R Series
12
A/D mode register (AMR)
A/D data register lower (ADRL)
A/D data register upper (ADRU)
Data
(464 digits)
V = 1
(bank = 1)
$000
$040
$050
$00A
$00B
$00E
$00F
W
W
R/W
R/W
W
R/W
R/W
W
W
R/W
R/W
W
R/W
R/W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
W
R/W
$090
$25F
$3C0
$260
RAM-mapped registers
RAM address
RAM address
Memory registers (16 digits)
LCD display area (52 digits)
Not used
Data (464 digits 3)
V = 0 (bank 0)
V = 1 (bank 1)
V = 2 (bank 2)
Data (352 digits)
Stack (64 digits)
Interrupt control bits area
Port mode register A (PMRA)
Serial mode register A (SMRA)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B1 (TMB1)
Timer B (TRBL/TWBL)
(TRBU/TWBU)
Miscellaneous register (MIS)
Timer mode register C1 (TMC1)
Timer C (TRCL/TWCL)
(TRCU/TWCU)
Timer mode register D1 (TMD1)
Timer D (TRDL/TWDL)
(TRDU/TWDU)
Timer mode register B2 (TMB2)
Timer mode register C2 (TMC2)
Timer mode register D2 (TMD2)
Register flag area
Port R0 DCR (DCR0)
Port R1 DCR (DCR1)
Port R2 DCR (DCR2)
Port R3 DCR (DCR3)
Port R4 DCR (DCR4)
Port R5 DCR (DCR5)
Port R6 DCR (DCR6)
Port R7 DCR (DCR7)
Port D
0
–D
3
DCR (DCD0)
Port D
4
–D
7
DCR (DCD1)
Port D
8
and D
9
DCR (DCD2)
Not used
Not used
V register (V)
Data
(464 digits)
V = 0
(bank = 0)
The data area has three banks:
bank 0 (V = 0) to bank 2 (V = 2).
Two registers are mapped
on the same area.
10
11
14
15
Timer read register B lower (TRBL)
Timer read register B upper (TRBU)
Timer read register C lower (TRCL)
Timer read register C upper (TRCU)
Timer write register B lower (TWBL)
Timer write register B upper (TWBU)
Timer write register C lower (TWCL)
Timer write register C upper (TWCU)
R:
W:
R/W:
$090
Read only
Write only
Read/write
Data
(464 digits)
V = 2
(bank = 2)
Notes: 1.
2.
$011
$012
W
W
R
R
17
18
Timer read register D lower (TRDL)
Timer read register D upper (TRDU)
Timer write register D lower (TWDL)
Timer write register D upper (TWDU)
$084
R/W
R/W
R/W
R
R
$3FF
LCD control register (LCR)
LCD mode register (LMR)
LCD output register 1 (LOR1)
LCD output register 2 (LOR2)
LCD output register 3 (LOR3)
W
W
W
W
W
W
W
W
W
W
W
W
Port mode register B (PMRB)
Port mode register C (PMRC)
Detection edge select register 1 (ESR1)
Detection edge select register 2 (ESR2)
Serial mode register B (SMRB)
System clock select register (SSR)
Not used
Not used
*
2
*
1
$000
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$020
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$032
$033
$034
$035
$036
$037
$038
$03E
$03F
$01B
$01C
$01D
$01E
$01F
$031
Figure 2 RAM Memory Map