參數(shù)資料
型號: HD404654H
廠商: Hitachi,Ltd.
英文描述: 4-Bit Single-Chip Microcomputer
中文描述: 4位單片機(jī)
文件頁數(shù): 68/109頁
文件大?。?/td> 430K
代理商: HD404654H
HD404654 Series
68
STS wait state
(Octal counter = 000,
Transmit clock disabled)
Transmit clock wait state
(Octal counter = 000)
Trans
fer
state
(Octal counter = 000)
MCU reset
00
SM1A write
04
STS instruction
01
Transmit clock
02
8 transmit clocks
03
STS instruction (IFS1 1)
05
SM1A write (IFS1 1)
06
External clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
Transmit clock wait state
(Octal counter = 000)
Transfer state
(Octal counter = 000)
SM1A write
14
STS instruction
11
Transmit clock
12
15
STS instruction (IFS1 1)
8 transmit clocks
13
Internal clock mode
Continuous transmit
clock output state
(PMRA 0, 1 = 0, 0)
SM1A write
18
Transmit clock
17
16
Note: Refer to the Operating States section for the corresponding encircled numbers.
MCU reset
10
SM1A write (IFS1 1)
Figure 53 Serial Interface State Transitions
STS wait state: Serial interface 1 enters STS wait state by MCU reset (00, 10 in figure 53). In STS wait
state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then
executed (01, 11), serial interface 1 enters transmit clock wait state.
Transmit clock wait state: Transmit clock wait state is the period between STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)
increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the
serial interface in transfer state. However, note that if continuous clock output mode is selected in
internal clock mode, the serial interface does not enter transfer state but enters continuous clock output
state (17).
The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04,
14) in transmit clock wait state.
Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge
of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction
sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is
executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait
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