HD404654 Series
7
0
$000
$000
$003
$004
$005
$006
$007
$008
$009
64
80
576
960
1023
$040
$050
4
5
6
7
8
9
0
3
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
11
32
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
63
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$020
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$032
$033
$034
$035
$03F
$00E
$00F
W
W
R/W
R/W
W
W
R/W
R/W
W
R/W
R/W
W
W
W
W
W
W
W
W
W
W
R
R
W
$3C0
$240
RAM-mapped registers
Memory registers (MR)
Not used
Data (432 digits)
Not used
Stack (64 digits)
Interrupt control bits area
Port mode register A
Serial mode register 1A
Serial data register 1 lower
Serial data register 1 upper
Timer mode register A
Miscellaneous register
Timer mode register C1
Timer C
Timer mode register D2
Register flag area
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port D to D DCR
Port D to D DCR
Port D and D DCR
Not used
14
15
Timer read register C lower
Timer read register C upper
Timer write register C lower
Timer write register C upper
$090
R:
W:
R/W:
Read only
Write only
Read/Write
$011
$012
W
W
R
R
17
18
Timer read register D lower
Timer read register D upper
Timer write register D lower
Timer write register D upper
144
Timer mode register D1
Timer D
Timer mode register C2
R
W
W
W
Compare data register
Compare enable register
TG mode register
TG control register
27
31
$01F
$3FF
W
W
Port mode register B
Port mode register C
Detection edge select register 2
Serial mode register 1B
System clock select register 1
System clock select register 2
Not used
Not used
W
W
W
W
$031
53
Two registers are mapped
on the same area.
R/W
R/W
(PMRA)
(SM1A)
(SR1L)
(SR1U)
(TMA)
(MIS)
(TMC1)
(TRCL/TWCL)
(TRCU/TWCU)
(TMD1)
(TRDL/TWDL)
(TRDU/TWDU)
Not used
(TMC2)
(TMD2)
(CDR)
(CER)
(TGM)
(TGC)
(PMRB)
(PMRC)
(SM1B)
(SSR1)
(SSR2)
(ESR2)
(DCD0)
(DCD1)
(DCD2)
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
Not used
(TRCL)
(TRCU)
(TRDL)
(TRDU)
(TWCL)
(TWCU)
(TWDL)
(TWDU)
Not used
Not used
Not used
Figure 2 RAM Memory Map