參數(shù)資料
型號(hào): HD151TS305RPEL
廠商: Renesas Technology Corp.
英文描述: Spread Spectrum Clock for EMI Solution
中文描述: 擴(kuò)頻時(shí)鐘的EMI解決方案
文件頁數(shù): 8/10頁
文件大?。?/td> 85K
代理商: HD151TS305RPEL
HD151TS305RP
Rev.9.00 Jul. 07, 2004 page 8 of 9
4. Recommendation of Power–ON Sequence
We recommend usage as power–on sequence Vdd starting profile.
At the time of power–on starting, there is possibility for SSCCKOUT to fix Hi/Low level. Please refer Fig6–1 and
Fig6–2.
Upper 2.8V
delay
Input Timing of XIN
(XIN should be applied after Vdd
2.8V)
XIN
XOUT
Ref. Clock
VDD
XIN
Power
ON
Fig 6–1 In case of reference clock input
2.8V
(Vdd rising time should be applied over 3.5V/msec)
XIN
XOUT
VDD
XIN
Minimal Rising Time
Power
ON
Over 3.5V/msec
X' tal
Fig 6–2 In case of X’tal reference input
5. Cycle to Cycle Jitter
We have guaranteed that cycle to cycle jitter will be less than |300ps| at XIN=18MHz, Vdd=3.3V. In case of using XIN
will be less than 15MHz, the cycle to cycle jitter may be over |300ps|. Please notice to consider this point.
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