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參數(shù)資料
| 型號： | HD151BF854SSEL |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | 2.5 V PLL Clock Buffer for DDR Application |
| 中文描述： | 2.5伏PLL時(shí)鐘緩沖器為DDR應(yīng)用 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 54K |
| 代理商： | HD151BF854SSEL |
HD151244
Octal Buffers/Line Drivers With 3 State Outputs
ADE-205-596 (Z)
1st. Edition
Dec. 2000
Description
The HD151244 using CMOS process, provides high speed and high drivability equivalent to HD74LS240
with super low power dissipation. The device has eight inverter drivers (three state outputs) in 20 pin
package. Each four drivers construct a group and the two groups are controlled separately by 1
G
and 2
G
which enable the output at low level. Power up down protection function keeps the output in high
impedance state at low V
CC
regardless of the state in enable inputs.
Features
High speed
High output current
tpd = 10 ns (Typ)
I
OH
= –15 mA
I
OL
= 24 mA
Both input and output is TTL level
Wide operating temperature: Ta = –40 to +85°C
Both input and output is high impedance state at supply off
The function provides power up down protection
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| HD151BF860 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Datasheet|ADE-205-716|JAN.31.03|61K |
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| HD151TS201ATEL | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Mother Board Clock Generator for Intel P4 Chipset Banias and Dothan processor / ODEM and MONTARA-GM chip set |
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