12
AC Electrical Specifications
V
CC
= 5V
±
10%, T
A
= -40
o
C to +85
o
C (HD-15530-9)
T
A
= -55
o
C to +125
o
C (HD-15530-8)
HD-15531
SYMBOL
PARAMETER
HD-15531B
UNITS
TEST CONDITIONS
(NOTE 2)
MIN
MAX
MIN
MAX
ENCODER TIMING
FEC
Encoder Clock Frequency
-
15
-
30
MHz
V
CC
= 4.5V and 5.5V, C
L
= 50pF
FESC
Send Clock Frequency
-
2.5
-
5.0
MHz
V
CC
= 4.5V and 5.5V, C
L
= 50pF
FED
Encoder Data Rate
-
1.25
-
2.5
MHz
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TMR
Master Reset Pulse Width
150
-
150
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TE1
Shift Clock Delay
-
125
-
80
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TE2
Serial Data Setup
75
-
50
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TE3
Serial Data Hold
75
-
50
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TE4
Enable Setup
90
-
90
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TE5
Enable Pulse Width
100
-
100
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TE6
Sync Setup
55
-
55
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TE7
Sync Pulse Width
150
-
150
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TE8
Send Data Delay
0
50
0
50
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TE9
Bipolar Output Delay
-
130
-
130
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TE10
Enable Hold
10
-
10
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TE11
Sync Hold
95
-
95
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
DECODER TIMING
FDC
Decoder Clock Frequency
-
15
-
30
MHz
V
CC
= 4.5V and 5.5V, C
L
= 50pF
FDS
Decoder Sync Clock
-
2.5
-
5.0
MHz
V
CC
= 4.5V and 5.5V, C
L
= 50pF
FDD
Decoder Data Rate
-
1.25
-
2.5
MHz
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TDR
Decoder Reset Pulse Width
150
-
150
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TDRS
Decoder Reset Setup Time
75
-
75
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TDRH
Decoder Reset Hold Time
10
-
10
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TMR
Master Reset Pulse
150
-
150
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TD1
Bipolar Data Pulse Width
TDC + 10
(Note 1)
-
TDC + 10
(Note 1)
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TD3
One Zero Overlap
-
TDC - 10
(Note 1)
-
TDC - 10
(Note 1)
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TD6
Sync Delay (ON)
-20
110
-20
110
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TD7
Take Data Delay (ON)
0
110
0
110
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TD8
Serial Data Out Delay
-
80
-
80
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TD9
Sync Delay (OFF)
0
110
0
110
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TD10
Take Data Delay (OFF)
0
110
0
110
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TD11
Valid Word Delay
0
110
0
110
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TD12
Sync Clock to Shift Clock
Delay
-
75
-
75
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
TD13
Sync Data Setup
75
-
75
-
ns
V
CC
= 4.5V and 5.5V, C
L
= 50pF
NOTES:
1. TDC = Decoder clock period = 1/FDC.
2. AC Testing as follows: Input levels: V
IH
= 70% V
CC
, V
IL
= 20% V
CC
; Input rise/fall times driven at 1ns/V; Timing Reference
levels: V
CC
/2; Output load: C
L
= 50pF.
HD-15531