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參數(shù)資料
| 型號(hào)： | HD1-15530-9 |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 網(wǎng)絡(luò)接口 |
| 英文描述： | CMOS Manchester Encoder-Decoder |
| 中文描述： | DATACOM, MANCHESTER ENCODER/DECODER, CDIP24 |
| 封裝： | CERDIP-24 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 169K |
| 代理商： | HD1-15530-9 |
5-143
Block Diagrams
ENCODER
DECODER
GND
MASTER RESET
SEND CLK IN
÷
6 OUT
BIT
COUNTER
CHARACTER
FORMER
12
13
22
14
÷
6
ENCODER
CLK
23
÷
2
21
2
18
19
20
15
17
SEND
DATA
SERIAL
DATA IN
ENCODER
ENABLE
SYNC
SELECT
ENCODER
SHIFT CLK
16
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
24
OUTPUT
INHIBIT
V
CC
7
6
UNIPOLAR
DATA IN
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
DECODER
CLK
MASTER
RESET
8
TRANSITION
FINDER
SYNCHRONIZER
5
13
DECODER
RESET
11
BIT
COUNTER
BIT
RATE
CLK
PARITY
CHECK
9
1
DECODER
SHIFT
CLK
CHARACTER
IDENTIFIER
10
3
VALID
WORD
SERIAL
DATA OUT
COMMAND/
DATA SYNC
TAKE
DATA
4
Pin Description
PIN
NUMBER
TYPE
NAME
SECTION
DESCRIPTION
1
O
VALID WORD
Decoder
Output high indicates receipt of a valid word, (valid parity and no Manches-
ter errors).
2
O
ENCODER SHIFT
CLOCK
Encoder
Output for shifting data into the Encoder. The Encoder samples SDI on the
low-to-high transition of Encoder Shift Clock.
3
O
TAKE DATA
Decoder
Output is high during receipt of data after identification of a sync pulse and
two valid Manchester data bits.
4
O
SERIAL DATA OUT
Decoder
Delivers received data in correct NRZ format.
5
I
DECODER CLOCK
Decoder
Input drives the transition finder, and the synchronizer which in turn
supplies the clock to the balance of the decoder, input a frequency equal to
12X the data rate.
6
I
BIPOLAR ZERO IN
Decoder
A high input should be applied when the bus is in its negative state. This pin
must be held high when the Unipolar input is used.
7
I
BIPOLAR ONE IN
Decoder
A high input should be applied when the bus is in its positive state. This pin
must be held low when the Unipolar input is used.
8
I
UNLPOLAR DATA IN
Decoder
With pin 6 high and pin 7 low, this pin enters unipolar data into the transition
finder circuit. If not used this input must be held low.
9
O
DECODER SHIFT
CLOCK
Decoder
Output which delivers a frequency (DECODER CLOCK
÷
12), synchro-
nized by the recovered serial data stream.
10
O
COMMAND SYNC
Decoder
Output of a high from this pin occurs during output of decoded data which
was preceded by a Command (or Status) synchronizing character. A low
output indicates a Data synchronizing character.
11
I
DECODER RESET
Decoder
A high input to this pin during a rising edge of DECODER SHIFT CLOCK
resets the decoder bit counting logic to a condition ready for a new word.
12
I
GROUND
Both
Ground Supply pin.
13
I
MASTER RESET
Both
A high on this pin clears 2:1 counters in both Encoder and Decoder, and
resets the
÷
6 circuit.
14
O
÷
6 OUT
Encoder
Output from 6:1 divider which is driven by the ENCODER CLOCK.
15
O
BIPOLAR ZERO OUT
Encoder
An active low output designed to drive the zero or negative sense of a
bipolar line driver.
16
I
OUTPUT INHIBIT
Encoder
A low on this pin forces pin 15 and 17 high, the inactive states.
17
O
BIPOLAR ONE OUT
Encoder
An active low output designed to drive the one or positive sense of a bipolar
line driver.
HD-15530
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD1-15530B3976 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HD1-15530B3976 DIE | 制造商:Harris Corporation 功能描述: |
| HD1-15531 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ENCODER/DECODER|CMOS|DIP|40PIN|CERAMIC |
| HD1-15531/883 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS Manchester Encoder-Decoder |
| HD1-15531-2 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Logic IC |
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