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參數(shù)資料
| 型號(hào)： | HCTS574D |
| 廠商： | Intersil Corporation |
| 英文描述： | Hex Inverters 14-CDIP -55 to 125 |
| 中文描述： | 輻射加固八路D類觸發(fā)器，三態(tài)，上升沿觸發(fā) |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 135K |
| 代理商： | HCTS574D |
694
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS574DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
20 Lead SBDIP
HCTS574KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
20 Lead Ceramic Flatpack
HCTS574D/Sample
+25
o
C
Sample
20 Lead SBDIP
HCTS574K/Sample
+25
o
C
Sample
20 Lead Ceramic Flatpack
HCTS574HMSR
+25
o
C
Die
Die
HCTS574MS
Radiation Hardened Octal D-Type
Flip-Flop, Three-State, Positive Edge Triggered
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20
TOP VIEW
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
D0
D1
D2
D3
D4
D6
D5
D7
GND
VCC
Q1
Q2
Q3
Q0
Q4
Q5
Q6
Q7
CP
2
3
4
5
6
7
8
9
10
1
20
19
18
17
16
15
14
13
12
11
OE
D0
D1
D2
Q3
Q4
D5
D6
Q7
GND
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
Features
3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-
Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Bus Driver O11utputs - 15 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCTS574MS is a Radiation Hardened non-inverting
octal D-type, positive edge triggered flip-flop with three-stateable
outputs. The HCTS574MS utilizes advanced CMOS/SOS
technology. The eight flip-flops enter data into their registers on
the LOW-to-HIGH transition of the clock (CP). Data is also
transferred to the outputs during this transition. The output
enable (OE) controls the three-state outputs and is independent
of the register operation. When the output enable is high, the
outputs are in the high impedance state.
The HCTS574MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS574MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
August 1995
Spec Number
518629
File Number
2359.2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCTS574DMSR | Hex Inverters 14-CFP -55 to 125 |
| HCTS574K | Hex Inverters 20-LCCC -55 to 125 |
| HCTS574KMSR | Hex Inverters 14-CDIP -55 to 125 |
| HCTS574MS | Hex Inverters 14-CFP -55 to 125 |
| HCTS646KMSR | Radiation Hardened Octal Bus Transceiver/Register, Three-State |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCTS574DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered |
| HCTS574HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered |
| HCTS574K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered |
| HCTS574KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered |
| HCTS574MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered |
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