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參數(shù)資料
| 型號： | HCTS08DMSR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Radiation Hardened Quad 2-Input AND Gate |
| 中文描述： | HCT SERIES, QUAD 2-INPUT AND GATE, CDIP14 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-14 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 159K |
| 代理商： | HCTS08DMSR |
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
HCTS08MS
Radiation Hardened
Quad 2-Input AND Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
Functional Diagram
TRUTH TABLE
INPUTS
OUTPUTS
An
Bn
Yn
L
L
L
L
H
L
H
L
L
H
H
H
NOTE: L = Logic Level Low, H = Logic level High
A1
B1
Y1
A2
B2
Y2
GND
VCC
B4
A4
Y4
B3
A3
Y3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
A1
B1
Y1
A2
B2
Y2
GND
VCC
B4
A4
Y4
B3
A3
Y3
An
Bn
Yn
(1, 4, 9, 12)
(2, 5, 10, 13)
(3, 6, 8, 11)
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD(Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day
(Typ)
Dose Rate Survivability: >1 x 10
12
Rads (Si)/Sec
Dose Rate Upset >10
10
RAD(Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V
- VIH = VCC/2
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCTS08MS is a Radiation Hardened Quad 2-Input
AND Gate. A high on both inputs force the output to a High state.
The HCTS08MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS08MS is supplied in a 14 lead Ceramic Flatpack
Package (K suffix) or a 14 lead SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
SCREENING
LEVEL
PACKAGE
HCTS08DMSR
-55
o
C to +125
o
C
Intersil Class
S Equivalent
14 Lead SBDIP
HCTS08KMSR
-55
o
C to +125
o
C
Intersil Class
S Equivalent
14 Lead Ceramic
Flatpack
HCTS08D/
Sample
+25
o
C
Sample
14 Lead SBDIP
HCTS08K/
Sample
+25
o
C
Sample
14 Lead Ceramic
Flatpack
HCTS08HMSR
+25
o
C
Die
Die
Spec Number
518842
File Number
2136.2
August 1995
D
相關PDF資料 |
PDF描述 |
|---|---|
| HCTS08D | Radiation Hardened Quad 2-Input AND Gate |
| HCTS08K | Radiation Hardened Quad 2-Input AND Gate |
| HCTS08MS | Radiation Hardened Quad 2-Input AND Gate |
| HCTS08HMSR | Radiation Hardened Quad 2-Input AND Gate |
| HCTS08KMSR | Radiation Hardened Quad 2-Input AND Gate |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HCTS08HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input AND Gate |
| HCTS08K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input AND Gate |
| HCTS08KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input AND Gate |
| HCTS08MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input AND Gate |
| HCTS109D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip Flop |
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