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參數(shù)資料
| 型號： | HCT273 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs |
| 中文描述： | 八路D觸發(fā)器與普通時鐘和復(fù)位觸發(fā)器的輸入通道兼容輸入 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 152K |
| 代理商： | HCT273 |
MC74HCT273A
http://onsemi.com
3
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
Fig.
– 55 to
25
_C
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
1, 4
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
1, 4
25
28
35
ns
tPHL
Maximum Propagation Delay, Reset to Q
2, 4
25
28
35
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
1, 5
18
20
22
ns
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Gate)*
30
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to 25
_C
v 85_C
v 125_C
Symbol
Parameter
Fig.
Min
Max
Min
Max
Min
Max
Unit
tsu
Minimum Setup Time, Data to Clock
3
10
12
15
ns
th
Minimum Hold Time, Clock to Data
3
3.0
3.0
3.0
ns
trec
Minimum Recovery Time, Set or Reset Inactive to Clock
2
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
1
12
15
18
ns
tw
Minimum Pulse Width, Set or Reset
2
12
15
18
ns
tr, tf
Maximum Input Rise and Fall Times
1
500
500
500
ns
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