參數(shù)資料
型號: HCPL-314J
英文描述: 0.4 Amp Output Current IGBT Gate Drive Optocoupler(0.4 Amp 輸出電流 IGBT門驅(qū)動耦合器)
中文描述: 0.4安培輸出電流IGBT柵極驅(qū)動光電耦合器(0.4安培輸出電流IGBT的門驅(qū)動耦合器)
文件頁數(shù): 14/16頁
文件大?。?/td> 232K
代理商: HCPL-314J
14
CMR with the LED On
(CMR
H
)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED
current of 8 mA provides
adequate margin over the
maximum I
FLH
of 5 mA to
achieve 10 kV/
μ
s CMR.
CMR with the LED Off
(CMR
L
)
A high CMR LED drive
circuit must keep the LED off
(V
F
V
F(OFF)
) during common
mode transients. For example,
during a -dV
CM
/dt transient in
Figure 23, the current flowing
through C
LEDP
also flows
through the R
SAT
and V
SAT
of the
logic gate. As long as the low
state voltage developed across
the logic gate is less than V
F(OFF)
the LED will remain off and no
common mode failure will occur.
The open collector drive circuit,
shown in Figure 24, can not keep
the LED off during a +dV
CM
/dt
transient, since all the current
flowing through C
LEDN
must be
supplied by the LED, and it is not
recommended for applications
requiring ultra high CMR
1
performance. The alternative
drive circuit which like the
recommended application circuit
(Figure 19), does achieve ultra
high CMR performance by
shunting the LED in the off state.
IPM Dead Time and
Propagation Delay
Specifications
The HCPL-314J includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
high and low side power
transistors are off. Any overlap
in Ql and Q2 conduction will
result in large currents flowing
through the power devices from
the high-voltage to the low-
voltage motor rails. To minimize
dead time in a given design, the
turn on of LED2 should be
delayed (relative to the turn off
of LED1) so that under worst-
case conditions, transistor Q1
has just turned off when
transistor Q2 turns on, as shown
in Figure 26. The amount of
delay necessary to achieve this
condition is equal to the
maximum value of the
propagation delay difference
specification, PDD max, which is
specified to be 500 ns over the
operating temperature range of
-40
°
to 100
°
C.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but it
does not tell a designer what the
maximum dead time will be. The
maximum dead time is equivalent
to the difference between the
maximum and minimum
propagation delay difference
specification as shown in
Figure 27. The maximum dead
time for the HCPL-314J is 1
μ
s
(= 0.5
μ
s - (-0.5
μ
s)) over the
operating temperature range of
-40
°
C to 100
°
C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal
temperatures and test conditions
since the optocouplers under
consideration are typically
mounted in close proximity to
each other and are switching
identical IGBTs.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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HCPL-314J-000E 功能描述:高速光耦合器 0.4A IGBT Gate Drive RoHS:否 制造商:Avago Technologies 電流傳遞比: 最大波特率: 最大正向二極管電壓:1.75 V 最大反向二極管電壓:5 V 最大功率耗散:40 mW 最大工作溫度:+125 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-5 封裝:Tube
HCPL-314J-000E 制造商:Avago Technologies 功能描述:GATE DRIVE OPTOCOUPLERLF - LEAD FREE VE
HCPL-314J-500E 功能描述:高速光耦合器 0.4A IGBT Gate Drive RoHS:否 制造商:Avago Technologies 電流傳遞比: 最大波特率: 最大正向二極管電壓:1.75 V 最大反向二極管電壓:5 V 最大功率耗散:40 mW 最大工作溫度:+125 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-5 封裝:Tube
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