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參數(shù)資料
| 型號： | HCPL-2630TV |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS |
| 中文描述： | 高速- 10兆比特/秒邏輯門光電耦合器 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大小： | 256K |
| 代理商： | HCPL-2630TV |
1-157
Package Characteristics
All Typicals at T
A
= 25
°
C.
Parameter
Input-Output
Insulation
Sym.
I
I-O
*
Package
Single 8-Pin DIP
Single SO-8
Min.
Typ.
Max.
1
Units
μ
A
Test Conditions
45% RH, t = 5 s,
V
I-O
= 3 kV dc, T
A
= 25
°
C
RH
≤
50%, t = 1 min,
T
A
= 25
°
C
Fig.
Note
20, 21
Input-Output
Momentary With-
stand Voltage**
V
ISO
8-Pin DIP, SO-8
Widebody
OPT 020
2500
5000
5000
V rms
20, 21
20, 22
Input-Output
Resistance
R
I-O
8-Pin DIP, SO-8
Widebody
10
12
10
13
V
I-O
= 500 V dc
1, 20,
23
10
12
10
11
T
A
= 25
°
C
T
A
= 100
°
C
f = 1 MHz, T
A
= 25
°
C
Input-Output
Capacitance
C
I-O
8-Pin DIP, SO-8
Widebody
0.6
0.5
pF
1, 20,
23
0.6
Input-Input
Insulation
Leakage Current
I
I-I
Dual Channel
0.005
μ
A
RH
≤
45%, t = 5 s,
V
I-I
= 500 V
24
Resistance
(Input-Input)
R
I-I
Dual Channel
10
11
24
Capacitance
(Input-Input)
C
I-I
Dual 8-Pin DIP
Dual SO-8
0.03
0.25
pF
f = 1 MHz
24
*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0
°
C to 70
°
C. HP specifies -40
°
C to 85
°
C.
*
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),
your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
For 6N137, HCPL-2601/2611/2630/2631/4661 only.
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does
not exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does
not exceed 15 mA.
4. Derate linearly above 80
°
C free-air temperature at a rate of 2.7 mW/
°
C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1
μ
F ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 17. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The JEDEC registration for the 6N137 specifies a maximum I
OH
of 250
μ
A. HP guarantees a maximum I
OH
of 100
μ
A.
7. The JEDEC registration for the 6N137 specifies a maximum I
CCH
of 15 mA. HP guarantees a maximum I
CCH
of 10 mA.
8. The JEDEC registration for the 6N137 specifies a maximum I
CCL
of 18 mA. HP guarantees a maximum I
CCL
of 13 mA.
9. The JEDEC registration for the 6N137 specifies a maximum I
EL
of –2.0 mA. HP guarantees a maximum I
EL
of -1.6 mA.
10. The t
PLH
propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
11. The t
PHL
propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
12. t
PSK
is equal to the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at any given temperature and specified
test conditions.
13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
14. The t
ELH
enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V
point on the rising edge of the output pulse.
15. The t
EHL
enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point
on the falling edge of the output pulse.
16. CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state
(i.e., V
O
> 2.0 V).
17. CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., V
O
< 0.8 V).
18. For sinusoidal voltages, (|dV
CM
| / dt)
max
=
π
f
CM
V
CM
(p-p).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCPL2630V | 功能描述:高速光耦合器 2Ch 10MBit/s Optocpl Logic Gate Output RoHS:否 制造商:Avago Technologies 電流傳遞比: 最大波特率: 最大正向二極管電壓:1.75 V 最大反向二極管電壓:5 V 最大功率耗散:40 mW 最大工作溫度:+125 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-5 封裝:Tube |
| HCPL-2630V | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:High Speed-10 MBit/s Logic Gate Optocouplers |
| HCPL2630W | 功能描述:高速光耦合器 2Ch 10MBit/s Optocpl Logic Gate Output RoHS:否 制造商:Avago Technologies 電流傳遞比: 最大波特率: 最大正向二極管電壓:1.75 V 最大反向二極管電壓:5 V 最大功率耗散:40 mW 最大工作溫度:+125 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-5 封裝:Tube |
| HCPL-2630W | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:High Speed-10 MBit/s Logic Gate Optocouplers |
| HCPL2630WV | 功能描述:高速光耦合器 2Ch 10MBit/s Optocpl Logic Gate Output RoHS:否 制造商:Avago Technologies 電流傳遞比: 最大波特率: 最大正向二極管電壓:1.75 V 最大反向二極管電壓:5 V 最大功率耗散:40 mW 最大工作溫度:+125 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-5 封裝:Tube |
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