參數(shù)資料
型號(hào): HCPL-0721
英文描述: 40 ns Propagation Delay,CMOS Optocoupler(40 ns 傳播延遲,CMOS光耦合器)
中文描述: 40納秒的傳播延遲,光耦的CMOS(40納秒的傳播延遲,的CMOS光耦合器)
文件頁數(shù): 9/16頁
文件大?。?/td> 305K
代理商: HCPL-0721
9
Application Information
Bypassing and PC Board
Layout
The HCPL-772X/072X
optocouplers are extremely easy
to use. No external interface
circuitry is required because the
HCPL-772X/072X use high-speed
CMOS IC technology allowing
CMOS logic to be connected
directly to the inputs and outputs.
As shown in Figure 10, the only
external components required for
proper operation are two bypass
capacitors. Capacitor values
should be between 0.01
μ
F and
0.1
μ
F. For each capacitor, the
total lead length between both
ends of the capacitor and the
power-supply pins should not
exceed 20 mm. Figure 11
illustrates the recommended
printed circuit board layout for
the HPCL-772X/072X.
Figure 10. Recommended Printed Circuit Board Layout.
Figure 11. Recommended Printed Circuit Board Layout.
Propagation Delay, Pulse-
Width Distortion and
Propagation Delay Skew
Propagation Delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
tion delay from low to high (t
PLH
)
is the amount of time required for
an input signal to propagate to
the output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (t
PHL
) is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low. See
Figure 12.
Figure 12.
INPUT
t
PLH
t
PHL
OUTPUT
V
I
V
O
10%
90%
90%
10%
V
OH
2.5 V CMOS
V
OL
0 V
50%
5 V CMOS
7
5
6
8
2
3
4
1
GND
2
C1
C2
NC
V
DD2
NC
V
O
V
DD1
V
I
7
Y
C1, C2 = 0.01 μF TO 0.1 μF
GND
1
V
DD2
C1
C2
7
Y
V
O
GND
2
V
DD1
V
I
GND
1
C1, C2 = 0.01 μF TO 0.1 μF
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