參數(shù)資料
型號： HCPL-0302-060E
廠商： AGILENT TECHNOLOGIES INC
元件分類： 光電耦合器
英文描述： 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER
封裝： SO-8
文件頁數(shù)： 6/16頁
文件大?。?/td> 130K
代理商： HCPL-0302-060E
14
Dead Time and Propagation Delay
Specifications
The HCPL-3020 and HCPL-
0302 include a Propagation
Delay Difference (PDD)
specification intended to help
designers minimize “dead
time” in their power inverter
designs. Dead time is the time
high and low side power
transistors are off. Any
overlap in Ql and Q2
conduction will result in large
currents flowing through the
power devices from the high
voltage to the low-voltage
motor rails. To minimize dead
time in a given design, the
turn on of LED2 should be
delayed (relative to the turn
off of LED1) so that under
worst-case conditions,
transistor Q1 has just turned
off when transistor Q2 turns
on, as shown in Figure 24.
The amount of delay necessary
to achieve this condition is
equal to the maximum value
of the propagation delay
difference specification, PDD
max, which is specified to be
500 ns over the operating
temperature range of –40° to
100°C.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero,
but it does not tell a designer
what the maximum dead time
will be. The maximum dead
time is equivalent to the
difference between the
maximum and minimum
propagation delay difference
specification as shown in
Figure 25. The maximum dead
time for the HCPL-3020 and
HCPL-0302 is 1 ms (= 0.5 s
– (–0.5 s)) over the operating
temperature range of –40°C to
100°C.
CMR with the LED On (CMRH)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This
is achieved by overdriving the
LED current beyond the input
threshold so that it is not
pulled below the threshold
during a transient. A minimum
LED current of 7 mA provides
adequate margin over the
maximum IFLH of 6 mA to
achieve 10 kV/s CMR.
CMR with the LED Off (CMRL)
A high CMR LED drive circuit
must keep the LED off (VF -
VF(OFF)) during common mode
transients. For example,
during a -dVCM/dt transient in
Figure 21, the current flowing
through CLEDP also flows
through the RSAT and VSAT of
the logic gate. As long as the
low state voltage developed
across the logic gate is less
than VF(OFF) the LED will
remain off and no common
mode failure will occur.
The open collector drive
circuit, shown in Figure 22,
cannot keep the LED off
during a +dVCM/dt transient,
since all the current flowing
through CLEDN must be
supplied by the LED, and it is
not recommended for
applications requiring ultra
high CMR1 performance. The
alternative drive circuit, which
likes the recommended
application circuit (Figure 17),
does achieve ultra high CMR
performance by shunting the
LED in the off state.
Note that the propagation delays
used to calculate PDD and dead time
are taken at equal temperatures and
test conditions since the optocouplers
under consideration are typically
mounted in close proximity to each
other and are switching identical
IGBTs.
相關(guān)PDF資料
PDF描述
HCPL-2400 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 40 Mbps
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