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參數(shù)資料
| 型號： | HCF4724 |
| 英文描述： | 8 BIT ADDRESSABLE LATCH |
| 中文描述： | 8位可尋址鎖存 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 779K |
| 代理商： | HCF4724 |
1/14
October 2002
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SERIAL DATA INPUT - ACTIVE PARALLEL
OUTPUT
STORAGE REGISTER CAPABILITY -
MASTER CLEAR
CAN FUNCTION AS DEMULTIPLEXER
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QUIESCENT CURRENT SPECIFIED UP TO
20V
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
INPUT LEAKAGE CURRENT
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= 100nA (MAX) AT V
DD
= 18V T
A
= 25°C
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100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
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DESCRIPTION
HCF4724B is a monolithic integrated circuit
fabricated
in
Metal
technology available in DIP and SOP packages.
HCF4724B, an 8-bit addressable latch, is a
serial-input, parallel output storage register that
can perform a variety of functions. Data is input to
a particular bit in the latch when the bit is
addressed (by means of input A0, A1, A2) and
when WRITE DISABLE is at a low level. When
Oxide
Semiconductor
WRITE DISABLE is high, data entry is inhibited;
however, all 8 outputs can be continuously read
independent of WRITE DISABLE and address
inputs. A master RESET input is available, which
resets all bits to a logic "0" level when RESET and
WRITE DISABLE are at a high level. When
RESET is at a high level, and WRITE DISABLE is
at a low level, the latch acts as a 1-of-8
demultiplexer; the bit that is addressed has an
active output which follows the data input, while all
unaddressed bits are held to a logic "0" level.
HCF4724B
8 BIT ADDRESSABLE LATCH
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
SOP
HCF4724BEY
HCF4724BM1
HCF4724M013TR
DIP
SOP
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