參數(shù)資料
型號: HCF4517B
廠商: 意法半導體
英文描述: DUAL 64-STAGE STATIC SHIFT REGISTER
中文描述: 雙64 -階段靜態(tài)移位寄存器
文件頁數(shù): 1/12頁
文件大?。?/td> 244K
代理商: HCF4517B
HCC/HCF4517B
September 1988
DUAL 64-STAGE STATIC SHIFT REGISTER
.
CLOCK FREQUENCY 12MHz (TYP.) AT V
DD
=
.
THREE-STATE OUTPUTS
.
QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
.
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
.
5V, 10V, AND 15V PARAMETRIC RATINGS
.
INPUT CURREN OF 100nA AT 18V AND 25
°
C
FOR HCC DEVICE
.
100% TESTEDFOR QUIESCENTCURRENT
.
MEETSALLREQUIREMENTSOFJEDECTEN-
TATIVE STANDARD N
°
. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIESCMOS DEVICES”
10V
.
SCHMITT TRIGGER CLOCK INPUTS ALLOW
OPERATION WITH VERY SLOW CLOCK RISE
AND FALL TIMES
DESCRIPTION
The
HCC4517B
(extended temperature range)and
HCF4517B
(intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dualin-line plastic or ceramic package.
The
HCC/HCF4517B
dual 64-stage static shift reg-
ister consists of two independent registers each
having a clock,data, andwrite enable inputandout-
puts accessible at taps following the 16th, 32nd,
48th, and 64th stages. These taps also serve as
input points allowing data to be inputted atthe 17th,
33rd, and 49th stages when the write enable input
is a logic 1 andthe clock goes through a low-to-high
transition. The truth table indicates how the clock
and write enable inputs control the operation of the
HCC/HCF4517B
. Inputs at the intermediate taps
allow entry of 64 bits into the register with 16 clock
pulses. The3-stateoutputspermit connection ofthis
device to an external bus.
EY
(Plastic Package)
F
(Ceramic Package)
C1
(ChipCarrier)
ORDERCODES :
HCC4517BF
HCF4517BM1
HCF4517BC1
PIN CONNECTIONS
1/12
相關PDF資料
PDF描述
HCC4517B Dual 64-Stage Static Shift Regiater(雙64級靜態(tài)移位寄存器)
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相關代理商/技術參數(shù)
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HCF4518BE 制造商:SNT 功能描述:
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