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參數(shù)資料
| 型號： | HCF4042 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QUAD CLOCKED ”D” LATCH |
| 中文描述： | 四時(shí)鐘的“D”鎖存 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 301K |
| 代理商： | HCF4042 |
HCC/HCF4042B
June1989
QUAD CLOCKED ”D” LATCH
.
CLOCKPOLARITY CONTROL
.
Q ANDQ OUTPUTS
.
COMMON CLOCK
.
LOWPOWER TTL COMPATIBLE
.
STANDARDIZED
CHARACTERISTICS
.
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
.
5V, 10V, AND 15V PARAMETRIC RATINGS
.
INPUT CURRENT OF100nAAT 18V AND 25
°
C
FOR HCC DEVICE
.
100% TESTEDFOR QUIESCENTCURRENT
.
MEETSALLREQUIREMENTSOFJEDECTEN-
TATIVESTANDARDN
°
13A,”STANDARDSPE-
CIFICATIONS FOR DESCRIPTION OF ”B”
SERIESCMOS DEVICES”
SYMMETRICAL
OUTPUT
DESCRIPTION
The
HCC4042B
(extended temperature range) and
HCF4042B
(intermediate temperature range) are
monolithic integrated circuit, available in 16-lead
dual in-line plastic or ceramic package and plastic
micro package.
The
HCC/HCF4042B
types contain four latch cir-
cuits, each strobed by a common clock. Com-
plementary buffered outputs are available from
each circuit. The impedanceofthen-and p-channel
output devices is balanced and all outputs are elec-
trically identical.
Information presentat the data input is transferred
to outputs Q and Q during the CLOCK level which
is programmed by the POLARITY input. For PO-
LARITY= 0 thetransfer occursduring the0CLOCK
levelandfor POLARITY = 1 the transfer occursdur-
ing the1 CLOCKlevel. The outputs follow the data
input providing the CLOCK and POLARITY levels
defined above are present. When a CLOCKtransi-
tionoccurs (positive forPOLARITY=0andnegative
for POLARITY = 1) the information present at the
input during the CLOCK transition is retained at the
outputs until an opposite CLOCKtransition occurs.
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Plastic Chip Carrier)
ORDERCODES :
HCC4042BF
HCF4042BEY
HCF4042BM1
HCF4042BC1
PIN CONNECTIONS
1/13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCF4042BM1 | Cartridge Fuse; Fuse Type:Fast Acting; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Series:AGC RoHS Compliant: No |
| HCF4042B | QUAD CLOCKED ”D” LATCH |
| HCF4042BC1 | Differential Driver And Receiver Pair 8-PDIP 0 to 70 |
| HCF4042BEY | QUAD CLOCKED ”D” LATCH |
| HCC4042BF | Dual Line Driver 14-PDIP 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCF40424M013TR | 制造商: 功能描述: |
| HCF4042B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:QUAD CLOCKED ”D” LATCH |
| HCF4042B_01 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:QUAD CLOCKED D LATCH |
| HCF4042BC1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:QUAD CLOCKED ”D” LATCH |
| HCF4042BEY | 功能描述:閉鎖 Quad Clock "D" Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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