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參數(shù)資料
| 型號(hào)： | HCF40104 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| 中文描述： | 4位雙向通用移位寄存器 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 270K |
| 代理商： | HCF40104 |
HCC/HCF40102B
HCC/HCF40103B
8-STAGE PRESETTABLESYNCHRONOUS DOWN COUNTERS
DESCRIPTION
SYNCHRONOUS
PRESET
.
MEDIUM-SPEED OPERATION : f
CL
= 3.6MHz
(TYP.) @ V
DD
= 10V
.
CASCADABLE
.
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
.
5V, 10V AND 15V PARAMETRIC RATINGS
.
INPUT CURRENTOF100nAAT18VAND25
°
C
FOR HCC DEVICE
.
100% TESTEDFOR QUIESCENTCURRENT
.
MEETSALLREQUIREMENTSOFJEDECTEN-
TATIVE STANDARD N
o
. 13 A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIESCMOS DEVICES”
OR
ASYNCHRONOUS
June 1989
The
HCC40102B
,
HCC40103B
,(extended tempera-
turerange) and the
HCF40102B
,
HCF40103B
(inter-
mediate temperature range) aremonolithic integrated
circuits,available in 16-lead dual in-line plastic orce-
ramic
package.
The
HCC/HCF40103B
consistofan 8-stagesynchronous
downcounterwithasingleoutputwhichisactivewhen
the internal count is zero. The
HCC/HCF40102B
is
configured as two cascaded 4-bit BCD counters, and
the
HCC/HCF40103B
contains a single 8-bit binary
counter. Each typehas controlinputsforenabling or
disabling the clock, for clearing the counter to its
maximum count, and for presetting the counter
eithersynchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT out-
put are active-low logic. In normal operation, the
counter is decremented by one count on eachposi-
tive transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/CE)
input is high. The CARRY-OUT/ZERO-DETEC
(CO/ZD) output goes low when the count reaches
zero if the CI/CE input is low, and remains low for
one full clock period. When the SYNCHRONOUS
PRESET-ENABLE (SPE) input is low, data at the
JAM input is clocked into the counter on the next
positiveclocktransitionregardless ofthestateofthe
CI/CE
input.
When
PRESET-ENABLE (APE) input is low, data at the
HCC/HCF40102B
,
and
the
ASYNCHRONOUS
EY
(Plastic Package)
F
(Ceramic Package)
C1
(ChipCarrier)
ORDERCODES :
HCC401XXBF
HCF401XXBEY
HCF401XXBC1
PIN CONNECTIONS
40102B 2-DECADE BCD TYPE
40103B 8-BIT BINARY TYPE
1/13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCF40104BEY | 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| HCF40104BF | 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| HCF40194BEY | Quadruple Differential Line Receiver 16-SO 0 to 70 |
| HCF40194BF | Quadruple Differential Line Receiver 16-SO 0 to 70 |
| HCC40102BF | Synchronous Down Counter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCF40104B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| HCF40104BC1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| HCF40104BEY | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| HCF40104BF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| HCF40105 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:FIFO REGISTER |
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