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參數(shù)資料
| 型號(hào)： | HCF40101BM1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | COMPACT MC 10MBPS W/ INTERNAL PS UTP/FO-SC |
| 中文描述： | 9位奇偶產(chǎn)生器/校驗(yàn)器 |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大小： | 268K |
| 代理商： | HCF40101BM1 |
HCC/HCF40101B
June1989
9-BIT PARITY GENERATOR/CHECKER
.
STANDARDIZED
CHARACTERISTICS
.
QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
.
5V, 10V, AND 15V PARAMETRIC RATINGS
.
INPUT CURRENTOF100nA AT18V AND 25
°
C
FOR HCC DEVICE
.
100% TESTEDFOR QUIESCENTCURRENT
.
MEETSALLREQUIREMENTSOFJEDECTEN-
TATIVESTANDARDN
°
13A,”STANDARDSPE-
CIFICATIONS FOR DESCRIPTION OF ”B”
SERIESCMOS DEVICES”
SYMMETRICAL
OUTPUT
DESCRIPTION
The
HCC40101B
(extended temperature range)
and
HCF40101B
(intermediate temperature range)
are monolithic integrated circuits, available in 14-
lead dual in-line plastic or ceramic package and
plasticmicro package.
The
HCC/HCF40101B
is a 9-bit (8 data bits plus 1
parity bit) parity generator/checker. It may be used
to detect errors in data transmission or data retrie-
val. Odd and even outputs facilitate odd or even
parity generation and checking. When used as a
parity generator, a parity bit is supplied along with
the data to generate an even or odd parity output.
When used a parity checker, the received data bits
and parity bits are compared for correct parity. The
even or odd outputs are used to indicate an error in
the received data. Word-length capability is expan-
dable by cascading. The
HCC/HCF40101B
is also
provided with an inhibit control. If the inhibit control
is set at logical ”1”, the even and odd outputs go to
a logical ”0”.
EY
(Plastic Package)
F
(Ceramic Frit Seal Package)
M1
(Micro Package)
C1
(Plastic ChipCarrier)
ORDERCODES :
HCC40101BF
HCF40101BEY
HCF40101BM1
HCF40101BC1
PIN CONNECTIONS
1/11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCC40101B | T-NPN-SI GEN PURP AMP |
| HCC40101BF | Bipolar Transistor; Collector Emitter Voltage, Vceo:60V; Transistor Polarity:PNP; C-E Breakdown Voltage:60V; DC Current Gain Min (hfe):35; Collector Current:600mA |
| HCF40101 | 9-BIT PARITY GENERATOR/CHECKER |
| HCF40101BC1 | 9-BIT PARITY GENERATOR/CHECKER |
| HCF40101BEY | 9-BIT PARITY GENERATOR/CHECKER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCF40102 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| HCF40102B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| HCF40102BC1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Down Counter |
| HCF40102BEY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Down Counter |
| HCF40102BF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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