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參數(shù)資料
| 型號： | HCF40100BC1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER |
| 中文描述： | 32 -階段靜態(tài)左/右移位寄存器 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 287K |
| 代理商： | HCF40100BC1 |
HCC/HCF40100B
32-STAGESTATIC LEFT/RIGHT SHIFT REGISTER
.
FULLY STATIC OPERATION
.
SHIFT LEFT/SHIFT RIGHT CAPABILITY
.
MULTIPLEPACKAGE CASCADING
.
RECIRCULATE CAPABILITY
.
LIFO OR FIFO CAPABILITY
.
STANDARDIZED
CHARACTERISTICS
.
QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
.
5V, 10V, AND 15V PARAMETRIC RATINGS
.
INPUT CURRENTOF100nA AT18V AND 25
°
C
FOR HCC DEVICE
.
100% TESTEDFOR QUIESCENTCURRENT
.
MEETSALLREQUIREMENTSOFJEDECTEN-
TATIVE STANDARD N
o
. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIESCMOS DEVICES”
DESCRIPTION
The
HCC40100B
(extended temperature range)
and
HCF40100B
(intermediate temperature range)
are monolithic integrated circuits, available in 16-
lead dual in-line plastic or ceramic package and
plastic micro package. The
HCC/HCF40100B
is a
32-stage shift register containing 32D-typemaster-
slave flip-flops. The data present at the SHIFT-
RIGHT INPUT is transferred into the first register
stagesynchronously withthepositive CLOCKedge,
provided the LEFT/RIGHT CONTROL is at a low
level, the RECIRCULATE CONTROL is at a high
level, and the CLOCK INHIBIT is low. If the
LEFT/RIGHT CONTROL is at a high level and the
RECIRCULATE CONTROLis also high, dataat the
SHIFT-LEFT INPUTistransferred into the32ndreg-
ister stage synchronously with the positive CLOCK
transition, provided the CLOCK INHIBITis low. The
state of the LEFT/RIGHT CONTROL, RECIRCU-
LATE CONTROL,and CLOCK INHIBIT should not
bechanged whentheCLOCKishigh. Dataisshifted
one stage left or one stage right depending on the
state of the LEFT/RIGHT CONTROL, synchron-
ously with the positive CLOCK edge. Data clocked
intothefirstor32ndregister statesisavailable atthe
SHIFT-LEFT or SHIFT-RIGHT OUTPUT respec-
tively, on the next negative CLOCK transition (see
DataTransfer Table). No shiftingoccurs on the posi-
tive CLOCKedge if the CLOCK INHIBITline is at a
highlevel. WiththeRECIRCULATECONTROLlow,
SYMMETRICAL
OUTPUT
June 1989
EY
(Plastic Package)
C1
(Plastic Chip Carrier)
ORDER CODES :
HCC40100BF
HCF40100BEY
HCF40100BM1
HCF40100BC1
PIN CONNECTIONS
data in the 32nd stage is shifted into the first stage
when the LEFT/RIGHTCONTROL is low and from
the 1st stage to the 32nd stage when the
LEFT/RIGHT CONTROL ishigh.
M1
(Micro Package)
F
(Ceramic FritSeal Package)
1/13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCF40100BEY | Dual Line Driver 8-SOIC 0 to 70 |
| HCC40100B | 32-Stage Static Left/Right Shift Register(32級靜態(tài)左/右移位寄存器) |
| HCF40100B | 32-Stage Static Left/Right Shift Register(32級靜態(tài)左/右移位寄存器) |
| HCC40104B | Bipolar Transistor; Transistor Polarity:Dual P Channel; Power Dissipation:0.2W; C-E Breakdown Voltage:15V; DC Current Gain Min (hfe):25; Collector Current:0.25A; DC Current Gain Max (hfe):50; Power (Ptot):200mW |
| HCC40105B | FIFO REGISTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCF40100BEY | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER |
| HCF40100BM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER |
| HCF40101 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:9-BIT PARITY GENERATOR/CHECKER |
| HCF40101B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:9-BIT PARITY GENERATOR/CHECKER |
| HCF40101BC1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:9-BIT PARITY GENERATOR/CHECKER |
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