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參數(shù)資料
| 型號： | HCD66731A01BP |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display |
| 中文描述： | 點(diǎn)陣液晶顯示控制器/驅(qū)動器支持日語漢字，韓文字體顯示 |
| 文件頁數(shù)： | 84/131頁 |
| 文件大?。?/td> | 5332K |
| 代理商： | HCD66731A01BP |
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HD66730/HD66731
83
Transferring Serial Data
The HD66730/1 enters serial interface mode when the IM pin is set low. A three-line clock-synchronous
transfer method is used. The HD66730/1 receives serial input data (SID) and transmits serial output data
(SOD) by synchronizing with a transfer clock (SCLK) sent from the master side.
When the HD66730/1 interfaces with several chips, chip select pin (CS*) must be used. The transfer clock
(SCLK) input is activated by making chip select (CS*) low. In addition, the transfer counter of the
HD66730/1 can be reset and serial transfer synchronized by making chip select (CS*) high. Here, since the
data which was being sent at reset is cleared, restart the transfer from the first bit of this data. In a minimum
system where a single HD66730/1 interfaces to a single MPU, an interface can be constructed from the
transfer clock (SCLK) and serial input data (SID). In this case, chip select (CS*) should be fixed to low.
The transfer clock (SCLK) is independent of operational clock (CLK) of the HD66730/1. However, when
several instructions are continuously transferred, the instruction execution time determined by the
operational clock (CLK) (see Continuous Transfer) must be considered since the HD66730/1 does not have
an internal transmit/receive buffer.
Figure 20 shows the basic procedure for transferring serial data. To begin with, transfer the start byte. By
receiving five consecutive bits of 1 (synchronizing bit string) at the beginning of the start byte, the transfer
counter of the HD66730/1 is reset and serial transfer is synchronized. The 2 bits following the
synchronizing bit string (5 bits) specify transfer direction (R/
W
bit) and register select (RS bit). Be sure to
transfer 0 in the 8th bit.
After receiving the start byte, instructions are received and the data/busy flag is transmitted. When the
transfer direction and register select remain the same, data can be continuously transmitted or received.
The transfer protocol is described in detail in the following.
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