參數(shù)資料
型號： HCD66727A04BP
廠商： Hitachi,Ltd.
英文描述： Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver with Key Scan Function
中文描述： 低功耗點陣液晶顯示控制器/鍵掃描功能驅(qū)動程序
文件頁數(shù)： 83/97頁
文件大?。?/td> 513K
代理商： HCD66727A04BP
HD66727
83
Partial-Display-Off Function
The HD66727 can program the number of display lines (NL bits), divide the internal operating frequency
by four (OSC bit), and adjust the display contrast (CT bits). Combining these functions, the HD66727 can
turn off the second and/or subsequent lines, displaying only the characters in the first line to reduce internal
current consumption (partial-display-off function). This function is suitable for calendar or time display,
which needs to be continuous during system standby with minimal current consumption. Here, the second
to fourth non-displayed lines are constantly driven by the deselection level voltage, thus turning off the
LCD for the lines.
Note that internal clock frequency is reduced to a quarter, quadrupling execution time of each instruction;
MPU data transfer rate must be appropriately adjusted. Moreover, as being affected by the NL1 bit and the
OSC1 bit, the key-scan cycle for partial-display-off is not the same as that for normal display. Adjust the
key-scan cycle by the KF1 and KF0 bits.
Table 38 lists partial-display-off function specifications and Figure 49 shows a sample display using the
partial-display-off function
Table 38
Partial-Display-Off Function
Function Item
Normal 4-Line Display
Partially-Off Display
Character display
1st to 4th lines displayed
Only 1st line displayed
Segment display
Possible
Possible
Annunciator display
Possible
Possible
R-C oscillation frequency
160 kHz
160 kHz
Internal operating frequency
160 kHz (OSC = 0)
40 kHz (OSC = 1)
LCD single-line drive frequency
2.7 kHz (1/34 duty ratio)
0.7 kHz (1/10 duty ratio)
Frame frequency
78 Hz
66 Hz
Key scan cycle
320 to 2,560 clock cycles
(Clock cycle = 1 / internal
operating frequency)
160 to 1,280 clock cycles
(Clock cycle = 1 / internal
operating frequency)
Note:
Select an optimum LCD drive voltage (between V
and V5) for the multiplexing duty ratio used,
using a reference voltage input pin (Vci) for the booster or the contrast adjust bits (CT) .
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