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參數(shù)資料
| 型號： | HCD61203U |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Power Darlington Bipolar Transistor; Collector Emitter Voltage, Vceo:100V; Transistor Polarity:NPN; Power Dissipation:65W; C-E Breakdown Voltage:100V; DC Current Gain Min (hfe):100; Collector Current:10A; Package/Case:3-TO-220 |
| 中文描述： | （點(diǎn)陣圖形液晶顯示64通道通用驅(qū)動程序） |
| 文件頁數(shù)： | 27/30頁 |
| 文件大?。?/td> | 95K |
| 代理商： | HCD61203U |
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HD61203U
27
AC Characteristics (V
CC
= 2.7V to 5.5V, GND = 0V, Ta = –30 to +75
°
C)
*2
In the Slave Mode (M/S = GND)
0.7 V
CC
0.3 V
CC
t
f
t
r
t
r
t
f
t
DS
t
DH
t
WLCL2L
t
WHCL2H
t
WLCL2H
t
WHCL2L
0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
t
DD
t
DHW
0.7 V
CC
0.3 V
CC
CL2
(FCS = GND)
(Shift clock)
CL2
(FCS = V
CC
)
(Shift clock)
DL (SHL = V
CC
)
DR (SHL = GND)
Input data
DR (SHL = V
CC
)
DL (SHL = GND)
Output data
Item
Symbol
Min
Typ
Max
Unit
Note
CL2 low level width (FCS = GND)
t
WLCL2L
t
WLCL2H
t
WHCL2L
t
WHCL2H
t
DS
t
DH
t
DD
t
DHW
t
r
t
f
450
—
—
ns
CL2 high level width (FCS = GND)
150
—
—
ns
CL2 low level width (FCS = V
CC
)
CL2 high level width (FCS = V
CC
)
Data setup time
150
—
—
ns
450
—
—
ns
100
—
—
ns
Data hold time
100
—
—
ns
Data delay time
—
—
200
ns
1
Data hold time
10
—
—
ns
CL2 rise time
—
—
30
ns
CL2 fall time
Notes: 1. The following load circuit is connected for specification.
—
—
30
ns
30 pF (includes jig capacitance)
Output terminal
2. Specified at +75
°
C for die products.
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