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參數(shù)資料
| 型號(hào)： | HCD44780UA02 |
| 廠(chǎng)商： | Hitachi,Ltd. |
| 英文描述： | 320 x 240 pixel format, CFL backlight available with power harness |
| 中文描述： | 點(diǎn)陣式液晶顯示控制器/驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 25/59頁(yè) |
| 文件大?。?/td> | 316K |
| 代理商： | HCD44780UA02 |
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HD44780U
25
Table 6
Instructions (cont)
Code
Execution Time
(max) (when f
cp
or
f
OSC
is 270 kHz)
37
μ
s
t
ADD
= 4
μ
s*
Instruction RS
R/
W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
Write data
to CG or
DDRAM
1
0
Write data
Writes data into DDRAM or
CGRAM.
Read data
from CG or
DDRAM
1
1
Read data
Reads data from DDRAM or
CGRAM.
37
μ
s
t
ADD
= 4
μ
s*
I/D
I/D
S
S/C = 1: Display shift
S/C = 0:
Cursor move
R/L = 1:
Shift to the right
R/L = 0:
Shift to the left
DL
= 1:
8 bits, DL = 0: 4 bits
N
= 1:
2 lines, N = 0: 1 line
F
= 1:
5
×
10 dots, F = 0: 5
×
8 dots
BF
= 1:
Internally operating
BF
= 0: Instructions acceptable
— indicates no effect.
*
After execution of the CGRAM/DDRAM data write or read instruction, the RAM address counter
is incremented or decremented by 1. The RAM address counter is updated after the busy flag
turns off. In Figure 10, t
ADD
is the time elapsed after the busy flag turns off until the address
counter is updated.
= 1:
= 0:
= 1:
Increment
Decrement
Accompanies display shift
DDRAM: Display data RAM
CGRAM: Character generator
RAM
ACG:
CGRAM address
ADD:
DDRAM address
(corresponds to cursor
address)
AC: Address counter used for
both DD and CGRAM
addresses
Execution time
changes when
frequency changes
Example:
When f
cp
or f
OSC
is
250 kHz,
2 = 40
250
37
μ
s
×
μ
s
Note:
Busy state
Busy signal
(DB7 pin)
Address counter
(DB0 to DB6 pins)
t
ADD
A
A + 1
Note: t depends on the operation frequency
t = 1.5/(f or f ) seconds
Figure 10 Address Counter Update
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