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參數(shù)資料
| 型號： | HCD404889 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Low-Voltage AS Microcomputers with On-Chip LCD Circuit(片上LCD電路的低壓微計算機) |
| 中文描述： | 低電壓如同在微機芯片LCD電路（片上液晶顯示器電路的低壓微計算機） |
| 文件頁數(shù)： | 86/200頁 |
| 文件大?。?/td> | 633K |
| 代理商： | HCD404889 |
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HD404889/HD404899/HD404878/HD404868 Series
86
Timer B Operation
Free-running/reload timer:
Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected
by means of timer mode register B1 (TMB1).
Timer B is initialized to the value written to timer write register B (TWBL, TWBU) by software, and
counts up by 1 each time the input clock is input. When the input clock is input after the timer B value
reaches $FF, overflow output is generated. Timer B is then set to the value in timer write register B if
the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts
counting up again.
Overflow output sets the timer B interrupt request flag (IFTB). This flag is reset by the program or by
an MCU reset.
For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial
Values after MCU Reset.
External event counter operation:
When external event input is designated for the input clock, timer B operates as an external event
counter. When external event input is used, the R1
0
/EVNB pin is designated as the EVNB pin by port
mode register 2 (PMR2).
The external event detected edge for timer B can be designated as a falling edge, rising edge, or both
falling and rising edges in the input signal by means of timer mode register B2 (TMB2). If both falling
and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc.
Timer B counts up by 1 each time a falling edge is detected in the signal input at the EVNB pin. Other
operations are the same as for the free-running/reload timer function.
Timer output operation:
With timer B, the R13/TOB pin is designated as the TOB pin by the setting of bit 3 of port mode
register 2 (PMR2), and toggle waveform output or PWM waveform output can be selected by timer
mode register B2 (TMB2).
Toggle output:
With toggle output, the output level is changed upon input of the next clock pulse after the timer B
value reaches $FF. Use of this function in combination with the reload timer allows a clock signal
with any period to be output, enabling it to be used as buzzer output. The output waveform is
shown in figure 38 (1).
PWM output:
With PWM output, variable-duty pulses are output. The output waveform is as shown in figure 38
(2), according to the contents of timer mode register B1 (TMB1) and timer write register B (TWBL,
TWBU). When the waveform is output with bit 3 (TMB13) of timer mode register B1 cleared to 0,
the write to timer write register B to change the duty is effective from the next frame, whereas if the
waveform is output with the TMB13 bit set to 1 (reload setting), the next frame is output
immediately after the timer write register write.
Module standby:
With timer B, the supply of the system clock to the timer/counter can be halted by setting bit 0 of
module standby register 1 (MSR1: $00D) to 1. In the module standby state, the mode register value is
retained but the counter value is not guaranteed.
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